mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 114
mc68hc908gp20
Manufacturer Part Number
mc68hc908gp20
Description
M68hc08 Family Of 8-bit Microcontroller Units Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908GP20.pdf
(406 pages)
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Advance Information
114
to use as the source for the base clock. (See
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See
The following conditions apply when the PLL is in automatic bandwidth
control mode:
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below
f
BUSMAX
•
•
•
•
•
7.7 Interrupts
The ACQ bit (See
read-only indicator of the mode of the filter. (See
Acquisition and Tracking
The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See
Specifications
The LOCK bit is a read-only indicator of the locked state of the
PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See
Specifications
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See
Control
.
Register.)
for information and precautions on using interrupts.)
for more information.)
for more information.)
7.6.2 PLL Bandwidth Control
7.9 Acquisition/Lock Time
7.9 Acquisition/Lock Time
Modes.)
7.4.8 Base Clock Selector
MC68HC908GP20
Freescale Semiconductor
7.4.4
Register.) is a
7.6.1 PLL
—
Rev 2.1
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