mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 330

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

20.9 Interrupts
Advance Information
330
NOTE:
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing mechanism must occur
with no MODF condition existing or else the flag is not cleared.
Four SPI status flags can be enabled to generate CPU interrupt
requests.
SPTE
SPRF
OVRF
MODF
Transmitter empty
Receiver full
Overflow
Mode fault
Flag
Table 20-2. SPI Interrupts
SPI transmitter CPU interrupt request
SPI receiver CPU interrupt request
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
(DMAS = 0, SPTIE = 1, SPE = 1)
(DMAS = 0, SPRIE = 1)
Request
MC68HC908GP20
Freescale Semiconductor
—
Rev 2.1