mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 298

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

19.5.2 SIM Counter During Stop Mode Recovery
19.5.3 SIM Counter and Reset States
19.6 Exception Control
19.6.1 Interrupts
Advance Information
298
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.
External reset has no effect on the SIM counter. (See
for details.) The SIM counter is free-running after all reset states. (See
19.4.2 Active Resets from Internal Sources
internal reset recovery sequences.)
Normal, sequential program execution can be changed in three different
ways:
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
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Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
for counter control and
MC68HC908GP20
Freescale Semiconductor
19.7.2 Stop Mode
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Rev 2.1