mc68hc908qz16 Freescale Semiconductor, Inc, mc68hc908qz16 Datasheet - Page 69
mc68hc908qz16
Manufacturer Part Number
mc68hc908qz16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908QZ16.pdf
(314 pages)
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4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, and the VCO power-of-two range selector bits.
Freescale Semiconductor
NOTES:
Addr.
$003A
$003B
$0036
$0037
$0038
$0039
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL Multiplier Select High
PLL Multiplier Select Low
PLL VCO Select Range
PLL Bandwidth Control
Register Name
PLL Control Register
Address:
Reserved Register
Register (PBWC)
Register (PMSH)
Register (PMRS)
Reset:
Register (PMSL)
Read:
Write:
See page 69.
See page 71.
See page 72.
See page 73.
See page 73.
(PCTL)
$0036
PLLIE
Bit 7
0
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
= Unimplemented
Figure 4-4. PLL Control Register (PCTL)
Figure 4-3. CGM I/O Register Summary
PLLF
6
0
PLLIE
AUTO
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
PLLON
5
1
= Unimplemented
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
BCS
4
0
PLLON
MUL5
VRS5
ACQ
5
1
0
0
0
0
0
0
0
R
R
3
0
MUL4
VRS4
BCS
R
4
0
0
0
0
0
0
0
0
0
= Reserved
= Reserved
R
2
0
MUL11
MUL3
VRS3
R
R
3
0
0
0
0
0
0
0
VPR1
1
0
MUL10
MUL2
VRS2
R
R
2
0
0
0
0
0
0
0
VPR0
Bit 0
0
VPR1
MUL9
MUL1
VRS1
R
1
0
0
0
0
0
0
0
CGM Registers
VPR0
MUL8
MUL0
VRS0
Bit 0
R
R
0
0
0
0
0
1
69
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