mc68hc908qz16 Freescale Semiconductor, Inc, mc68hc908qz16 Datasheet - Page 159

• Manufacturer Part Number: mc68hc908qz16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Figure 13-4
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
13.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Freescale Semiconductor
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
PTAPUE
Bit
X
1
0
shows the port A I/O logic.
Address:
DDRA
Reset:
Read:
Write:
Bit
0
0
1
Figure 13-5. Port A Input Pullup Enable Register (PTAPUE)
DD
PTAPUEx
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
PTAPUE7
$000D
by internal pullup device
Bit 7
0
PTA
X
Bit
X
X
(1)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
PTAPUE6
6
0
Input, Hi-Z
Input, V
Table 13-2. Port A Pin Functions
RESET
Figure 13-4. Port A I/O Circuit
I/O Pin
Output
Mode
V
DD
PTAPUE5
INTERNAL
PULLUP
DEVICE
DD
5
0
(2)
(4)
Table 13-2
PTAPUE4
DDRAx
Accesses to DDRA
PTAx
4
0
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Read/Write
PTAPUE3
summarizes the operation of the port A pins.
3
0
PTAPUE2
2
0
PTA7–PTA0
Read
PTAPUE1
Pin
Pin
1
0
Accesses to PTA
PTAPUE0
Bit 0
PTAx
0
PTA7–PTA0
PTA7–PTA0
PTA7–PTA0
Write
Port A
(3)
(3)
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