mc68hc908qz16 Freescale Semiconductor, Inc, mc68hc908qz16 Datasheet - Page 266
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mc68hc908qz16
Manufacturer Part Number
mc68hc908qz16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908QZ16.pdf
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Timer Interface Module (TIM)
PS[2:0] — Prescaler Select Bits
19.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
266
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 19-2
Address: T1CNTH, $0021 and T2CNTH, $002C
Address: T1CNTL, $0022 and T2CNTL, $002D
shows. Reset clears the PS[2:0] bits.
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Reset:
Reset:
Read:
Read:
Write:
Write:
PS2
Bit 15
0
0
0
0
1
1
1
1
Bit 7
Bit 7
Bit 7
0
0
Figure 19-6. TIM Counter Registers High (TCNTH)
Figure 19-7. TIM Counter Registers Low (TCNTL)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
= Unimplemented
= Unimplemented
14
PS1
6
0
6
6
0
0
0
1
1
0
0
1
1
Table 19-2. Prescaler Selection
13
5
0
5
5
0
PS0
0
1
0
1
0
1
0
1
NOTE
12
4
0
4
4
0
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Not available
11
3
0
3
3
0
TIM Clock Source
10
2
0
2
2
0
1
9
0
1
1
0
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
0
0
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