z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 158
z80189
Manufacturer Part Number
z80189
Description
Z80180, Z8s180, Z8l180 Mpu Operation
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z80189.pdf
(326 pages)
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PS
1
Prescaler
Divide
Ratio
f ¸ 30
Baud Rate Generator
DR Rate
0
1
Sampling
Rate
16
64
Table 19.
The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes.
The first is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a 16-bit time
constant register, and is identical to the DMSCC BRG. This feature allows
SS2 SS1 SS0 Divide
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(Z8S180/Z8L180-Class Processors Only)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Baud Rate
ASCI Baud Rate Selection (Continued)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ratio
¸1
¸1
16
32
64
—
16
32
64
—
2
4
8
2
4
8
General
f ¸ 1920
Divide
Ratio
f ¸ 480
122880
fc ¸ 16
fc ¸ 64
15360
30720
15360
30720
61440
1920
3840
7680
3840
7680
960
f = 6.144
MHz
Baud Rate (Example)
—
—
f = 4.608
MHz
Family MPU User Manual
(BPS)
9600
4800
2400
1200
2400
1200
37.5
600
300
150
600
300
150
—
75
—
f = 3.072
MHz
—
—
UM005003-0703
I/O
0
0
I
I
Z8018x
CKA
Clock
Frequency
f ¸ 30
60
120
240
480
960
1920
fc
f ¸ 30
60
120
240
480
960
1920
fc
143
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