z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 38
z80189
Manufacturer Part Number
z80189
Description
Z80180, Z8s180, Z8l180 Mpu Operation
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z80189.pdf
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A0
D0
IORQ
WAIT
–
–
A19
WR
Phi
RD
D7
T1
Figure 13.
Basic Instruction Timing
An instruction may consist of a number of machine cycles including Op
Code fetch, operand fetch, and data read/write cycles. An instruction may
also include cycles for internal processes which make the bus IDLE. The
example in Figure 14 illustrates the bus timing for the data transfer
instruction LD (IX+d),g.
I/O address
T2
I/O Read Cycle
I/O Read/Write Timing Diagram
TW
Read data
T3
T1
Family MPU User Manual
Write data
I/O Write Cycle
I/O address
T2
TW
UM005003-0703
Z8018x
T3
23
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