atam510 ATMEL Corporation, atam510 Datasheet - Page 36

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atam510

Manufacturer Part Number
atam510
Description
Marc4 4-bit Mtp Universal Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
36
ATAM510
Each timer represents a single maskable interrupt source (T0INT and T1INT), the priority of
which can be configured under program control. A Timer 0 interrupt can be caused by any of
three conditions (overflow, compare or end-of-measurement). The associated status register
(T0SR) differentiates between these. A status register is not necessary in Timer 1 as an interrupt
is caused only on a compare condition.
Figure 3-11. Timer/Counter Module
SUBCL
SUBCL
SYSCL
SYSCL
T0IN1
T0IN0
T1IN
TCCR
MUX
4:1
MUX
4:1
< = CPU Read/write registers
TCMO
rst
ck
Prescaler
T1CR
ck
rst
Prescaler
T0OUT0
MUX
T0CR
8:1
MUX
8:1
T1OUT
T0MO
MUX
2:1
control
control
Reload
control
Gating
Clock
16-bit mode
T1MO
Reload
control
control
Clock
up/down
reset
Int. enable
reset
Compare
Compare
Capture
up/down
carr
register
register
counter
T0CA
T0CP
y
Compare
Compare
up/down
Int. enable
register
Capture
register
counter
T1CA
T1CP
overflow
overflow
register
Status
Output
control
Output
control
T0SR
Int
Int
measu-
rement
Timer 0
end-of-
Timer 1
4711B–4BMCU–01/05
T0OUT1
T0OUT0
T0INT
T1INT
T1OUT

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