atam510 ATMEL Corporation, atam510 Datasheet - Page 13

• Manufacturer Part Number: atam510
• Description: Marc4 4-bit Mtp Universal Microcontroller
• Manufacturer: ATMEL Corporation

2.6
2.6.1
2.6.2
2.6.3
4711B–4BMCU–01/05
Hardware Reset
Power-on Reset
External Reset (NRST)
Coded Reset (Port A)
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated
independent of the current program state. It can be triggered by either initial supply power-up, a
short collapse of the power supply, a watchdog time-out, activation of the NRST input, or the
occurrence of a coded reset on Port A (see
A master reset activation will reset the interrupt enable flag, the interrupt pending registers the
interrupt active registers and initializes all on-chip peripherals. In this state all ports take on a
high resistance input status with deactivated pull-up and pull-down transistors (see
on page
When the reset condition disappears, the hardware configuration previously programmed in the
configuration EEPROM (see section “MTP Programming”) is loaded into the peripherals so that
all port characteristics and pull-up/downs reflect the programmed configuration. This configura-
tion period is immediately followed by a further reset delay time (approximately 80 ms), after
which a short call instruction (opcode C1h) to the EEPROM address 008h is performed. This
activates the initialization routine $RESET which in turn initializes all necessary RAM variables,
stack pointers and peripheral configuration registers.
Figure 2-7.
The fully integrated power-on reset circuit ensures that the core is held in a reset state until the
minimum operating supply voltage has been reached. A reset condition is also generated should
the supply voltage drop momentarily below the minimum operating supply.
An external reset can be triggered with the NRST pin. To activate an external reset, the pin
should be low for a minimum of 4 µs.
The coded reset circuit is connected directly to Port A terminals. By using a mask option, the
user can define a hardwired code combination (e.g., all pins low) which, if occurring on Port A,
will generate a reset in the same way as the NRST pin.
16)
NRST
Port A
Reset Configuration/Start-up Sequence
reset code
CODE
(1)
V
DD
Pull-up
Port A
I/O
Figure
Time out
2-7).
Power-on
Watch-
dog
reset
(1)
(1)
rst
= Configuration
Reset delay
timer
V
V
WD reset
SS
DD
CPU
ATAM510
CPU reset
Figure 2-9
13