atam510 ATMEL Corporation, atam510 Datasheet - Page 32
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atam510
Manufacturer Part Number
atam510
Description
Marc4 4-bit Mtp Universal Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.ATAM510.pdf
(72 pages)
- Current page: 32 of 72
- Download datasheet (2Mb)
3.2.8
3.3
32
Interval Timers/Prescaler
ATAM510
TIM1 - Dedicated Timer 1 I/O Pin
Figure 3-8.
TIM1 is a dedicated bi-directional I/O stage for signal communication to and from Timer 1 in the
timer/counter module (see
from the CPU. Direction control is performed from the timer/counter configuration registers.
The interval timers are based on a frequency divider for generating two independent time base
interrupts. It is driven by SUBCL generated by the clock module (see
consists of a 15-stage binary divider and two programmable multiplexers for selecting the appro-
priate interrupt frequencies for each interrupt source (see
multiplexer is completely independent and is controlled by the common Interval Timer Fre-
quency Select Register (ITFSR). Buffer registers store the respective frequency select codes
and ensure complete programming independence of each interrupt channel.
Interrupt masking and programming of the interrupt priority levels is performed with the aid of the
Interval Timer Interrupt Priority Register (ITIPR).
Bi-directional Pin TIM1
T1Dir (direction control)
T1IN (Timer 1 input)
T1OUT (Timer 1 output)
Figure
3-8). It has no I/O bus interface and is not directly accessible
(1)
Flash options
V
DD
(1)
(1)
Figure 3-9 on page
V
DD
Figure 2-9 on page
Pull-up
(1)
(1)
Pull-down
TIM1
4711B–4BMCU–01/05
33). Each
16) and
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