ade7566 Analog Devices, Inc., ade7566 Datasheet - Page 9

• Manufacturer Part Number: ade7566
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

TIMING SPECIFICATIONS
AC inputs during testing are driven at V
for Logic 1 and V
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a
100 mV change from the loaded V
C
V
Table 5. Clock Input (External Clock Driven XTAL1) Parameter
Parameter
t
t
t
t
t
1/t
1
Table 6. I
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
CK
CKL
CKH
CKR
CKF
BUF
L
H
SHD
DSU
DHD
RSU
PSU
R
F
SUP
The ADE7566/ADE7569 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the
Input filtering on both the SCLK and SDATA inputs suppresses noise spikes less than 50 ns.
system. The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR.
LOAD
DD
CORE
1
= 2.7 V to 3.6 V; all specifications T
for all outputs = 80 pF, unless otherwise noted.
2
SDATA (I/O)
C-Compatible Interface Timing Parameters (400 kHz)
SCLK (I)
t
PSU
DV
IL
maximum for Logic 0 as shown in Figure 2.
DD
Description
Bus-free time between stop condition and start condition
SCLK low pulse width
SCLK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Rise time of both SCLK and SDATA
Fall time of both SCLK and SDATA
Pulse width of spike suppressed
– 0.5V
0.45V
CONDITION
STOP
Description
XTAL1 period
XTAL1 width low
XTAL1 width high
XTAL1 rise time
XTAL1 fall time
Core clock frequency
PS
t
BUF
CONDITION
START
OH
/V
t
0.2DV
DSU
0.2DV
SWOUT
OL
TEST POINTS
MIN
level occurs as shown in Figure 2.
t
SHD
DD
to T
DD
− 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at V
– 0.1V
+ 0.9V
1
MSB
MAX
1
, unless otherwise noted.
Figure 2. Timing Waveform Characteristics
Figure 3. I
t
DHD
2 TO 7
2
C-Compatible Interface Timing
Rev. 0 | Page 9 of 136
t
V
L
LOAD
Min
0.032768
LSB
V
V
LOAD
LOAD
8
t
t
SUP
SUP
– 0.1V
+ 0.1V
t
H
t
DSU
32.768 kHz External Crystal
REFERENCE
ACK
9
POINTS
TIMING
t
RSU
6.26
9
9
Typ
30.52
6.26
1.024
t
DHD
REPEATED
START
S(R)
V
V
LOAD
LOAD
ADE7566/ADE7569
– 0.1V
– 0.1V
Max
4.096
t
F
V
MSB
LOAD
t
Typ
1.3
1.36
1.14
251.35
740
400
12.5
400
200
300
50
F
1
t
R
t
R
IH
minimum
Unit
μs
μs
μs
ns
ns
MHz
Unit
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns