ade7566 Analog Devices, Inc., ade7566 Datasheet - Page 115

• Manufacturer Part Number: ade7566
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

(SHIFT CLOCK)
UART OPERATION MODES
Mode 0 (Shift Register with Baud Rate Fixed at f
Mode 0 is selected when the SM0 and SM1 bits in the Serial
Communications Control Register Bit Description SFR (SCON,
0x98) are cleared. In this shift register mode, serial data enters
and exits through RxD. TxD outputs the shift clock. The baud
rate is fixed at f
received.
Transmission is initiated by any instruction that writes to the
Serial Port Buffer SFR (SBUF, 0x99). The data is shifted out of
the RxD line. The 8 bits are transmitted with the least significant
bit (LSB) first.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
data is clocked into the RxD line, and the clock pulses are
output from the TxD line as shown in Figure 97.
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, each frame consists of 10 bits transmitted
on TxD or received on RxD.
The baud rate is set by a timer overflow rate. Timer 1 or Timer 2
can be used to generate baud rates, or both timers can be used
simultaneously where one generates the transmit rate and the
other generates the receive rate. There is also a dedicated timer
for baud rate generation, the UART timer, which has a fractional
divisor to precisely generate any baud rate (see the UART Timer
Generated Baud Rates section).
Transmission is initiated by a write to the Serial Port Buffer SFR
(SBUF, 0x99). Next, a stop bit (1) is loaded into the ninth bit
position of the transmit shift register. The data is output bit-by-
bit until the stop bit appears on TxD and the transmit interrupt
flag (TI) is automatically set as shown in Figure 98.
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming that a valid start bit is detected, character
reception continues. The 8 data bits are clocked into the serial
port shift register.
(SCON.1)
(DATA OUT)
TxD
TI
RxD
TxD
START
BIT
D0
DATA BIT 0
CORE
Figure 97. 8-Bit Shift Register Mode
Figure 98. 8-Bit Variable Baud Rate
D1
/12. Eight data bits are transmitted or
D2
DATA BIT 1
D3
D4
D5
DATA BIT 6
READY FOR MORE DATA)
D6
(FOR EXAMPLE,
SET INTERRUPT
D7
STOP BIT
DATA BIT 7
CORE
/12)
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All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
•
•
If any of these conditions are not met, the received frame is
irretrievably lost, and the receive interrupt flag (RI) is not set.
If the received frame has met the previous criteria, the following
events occur:
•
•
•
Mode 2 (9-Bit UART with Baud Fixed at f
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at f
SMOD bit in the Program Control SFR (PCON, 0x87) doubles
the frequency to f
a start bit (0), 8 data bits, a programmable ninth bit, and a stop
bit (1). The ninth bit is most often used as a parity bit or as part
of a multiprocessor communication protocol, although it can be
used for anything, including a ninth data bit, if required.
To use the ninth data bit as part of a communication protocol for
a multiprocessor network such as RS-485, the ninth bit is set to
indicate that the frame contains the address of the device with
which the master would like to communicate. The devices on
the network are always listening for a packet with the ninth bit
set and are configured such that if the ninth bit is cleared, the
frame is not valid, and a receive interrupt is not generated. If the
ninth bit is set, all devices on the network receive the address and
obtain a receive character interrupt. The devices examine the
address and if it matches one of the device’s preprogrammed
addresses, that device configures itself to listen to all incoming
frames, even those with the ninth bit cleared. Because the master
has initiated communication with that device, all the following
packets with the ninth bit cleared are intended specifically for
that addressed device until another packet with the ninth bit set
is received. If the address does not match, the device continues
to listen for address packets.
If the extended UART is disabled (EXTEN = 0 in the CFG
SFR), RI must be 0 to receive a character. This ensures that
the data in the SBUF SFR is not overwritten if the last
received character has not been read.
If frame error checking is enabled by setting SM2, the
received stop bit must be set to receive a character. This
ensures that every character received comes from a valid
frame, with both a start bit and a stop bit.
The 8 bits in the receive shift register are latched into the
SBUF SFR.
The ninth bit (stop bit) is clocked into RB8 in the SCON SFR.
The receiver interrupt flag (RI) is set.
CORE
/32. Eleven bits are transmitted or received:
CORE
/64 by default, although setting the
ADE7566/ADE7569
CORE
/64 or f
CORE
/32)