ade7566 Analog Devices, Inc., ade7566 Datasheet - Page 41

• Manufacturer Part Number: ade7566
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Table 43. Interrupt Enable 3 SFR (MIRQENH, 0xDB)
Bit No.
7 to 6
5
4
3
2
1
0
ANALOG INPUTS
Each ADE7566/ADE7569 has two fully differential voltage
input channels. The maximum differential input voltage for
input pairs V
signal level on analog inputs for V
with respect to AGND.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the GAIN register in the
Energy Measurement Register List (see Table 37 and Figure 39).
Bit 0 to Bit 2 select the gain for the PGA in the current channel,
and Bit 5 to Bit 7 select the gain for the PGA in the voltage
channel. Figure 38 shows how a gain selection for the current
channel is made using the gain register.
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The gain register also selects the
ADC analog input range (see Figure 39). As mentioned
previously, the maximum differential input voltage is 0.4 V.
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Interrupt Enable Bit
P
/V
N
and I
P
/I
N
is ±0.4 V. In addition, the maximum
P
/V
N
Description
Reserved.
When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.
and I
P
/I
N
is ±0.4 V
Rev. 0 | Page 41 of 136
PGA 2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
V
V
V
IN
P
N
1
1
Figure 38. PGA in Current Channel
7
0
Figure 39. Analog Gain Register
7
0
6
0
6
0
GAIN REGISTER*
5
0
5
GAIN[7:0]
0
K × V
4
0
4
0
3
0
IN
3
0
2
0
CFSIGN_OPT
RESERVED
ADE7566/ADE7569
2
0
1
0
1
0
GAIN (K)
SELECTION
0
0
PGA 1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
0
0
ADDR:
0x1B