ade7566 Analog Devices, Inc., ade7566 Datasheet - Page 82

• Manufacturer Part Number: ade7566
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7566/ADE7569
INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 70 and Table 71. Most of the interrupts have
flags associated with them.
Table 70. Interrupt Flags
Interrupt Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ITEMP (Temperature ADC)
IPSM (Power Supply)
IADE (Energy Measurement DSP)
Table 71. Status Flags
Interrupt Source
ITEMP (Temperature ADC)
ISPI/I2CI
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
A functional block diagram of the interrupt system is shown in
Figure 83. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE7566/
ADE7569 from PSM2, a pending external interrupt is generated.
When the EX0 or EX1 bits in the Interrupt Enable SFR (IE, 0xA8)
are set to enable external interrupts, the program counter is
loaded with the IE0 or IE1 interrupt vector. The IE0 and IE1
interrupt flags in the TCON register are not affected by events
that occur when the 8052 MCU core is shut down during
PSM2. See the Power Supply Monitor Interrupt (PSM) section.
The RTC, temperature ADC, and I
such that pending interrupts cannot be cleared without entering
their respective interrupt service routines. Clearing the RTC
midnight flags and alarm flags does not clear a pending RTC
interrupt. Similarly, clearing the I
Flag
SPI2CSTAT
SPI2CSTAT
TIMECON.7
TIMECON.2
WDCON.2
2
C/SPI status bits in the SPI
Flag
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
T2CON.7
T2CON.6
IPSMF.6
MIRQSTL.7
2
C/SPI interrupts are latched
Bit Address
WDS
Bit Address
IE0
TF0
IE1
TF1
TI
RI
TF2
EXF2
FPSM
Temperature ADC Interrupt. Does not have a status flag associated with it.
SPI Interrupt Status Register.
RTC Midnight Flag.
RTC Alarm Flag.
Watchdog Timeout Flag.
Description
I
2
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C Interrupt Status Register.
Description
External Interrupt 0.
Timer 0.
External Interrupt 1.
Timer 1.
Transmit Interrupt.
Receive Interrupt.
Timer 2 Overflow Flag.
Timer 2 External Flag.
Temperature ADC Interrupt. Does not have an interrupt flag associated with it.
PSM Interrupt Flag.
Read MIRQSTH, MIRQSTM, MIRQSTL.
Interrupt Status SFR (SPISTAT, 0xEA) does not cancel a
pending I
until the RTC or I
respective interrupt service routines are entered shortly
thereafter.
Figure 83 shows how the interrupts are cleared when the
interrupt service routines are entered. Some interrupts with
multiple interrupt sources are not automatically cleared;
specifically the PSM, ADE, UART, and Timer 2 interrupt
vectors. Note that the INT0 and INT1 interrupts are only
cleared if the external interrupt is configured to be triggered by
a falling edge by setting IT0 in the Timer/Counter 0 and
Timer/Counter 1 Control SFR (TCON, 0x88). If INT0 or INT1
is configured to interrupt on a low level, the interrupt service
routine is reentered until the respective pin goes high.
2
C/SPI interrupt. These interrupts remain pending
2
C/SPI interrupt vectors are enabled. Their