pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 778

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.2.1 DCS Gate
2.3 Arbitration Algorithm
Table 1: Peripheral ID and Sub-Arbitration
The DCS gate is a simple connection between the DCS bus and the Hub. Any 32-bit
write transaction that is in the range of DCS_DRAM_LO to DCS_DRAM_HI causes a
write transaction to main memory via the DCS Gate. This is provided for booting
PNX15xx Series from EEPROM. The DCS_DRAM_LO and DCS_DRAM_HI
registers are located in the Global Registers; see
Resources
Series.
One of the most important purposes of the arbiter is to guarantee a high level of
quality of service to the DMA agents (PNX15xx Series modules). In technical terms
this means:
The arbiter is not optimized to process requests for memory access from CPUs.
Typically the performance of CPUs depends directly on the access latency to memory
and for this reason they require the lowest possible memory latency. To realize this
CPUs can best get their performance requirements via a private port on a multi-port
memory controller. Therefore, the CPUs are not connected to the arbiter and do not
route memory requests via the Hub.
To support the quality of service features as mentioned above the arbiter algorithm
consists of a combination of three basic arbitration mechanisms. These are:
TDMA
ID
0x3
0x4
0x5
0x6:0x7
•
•
•
•
•
•
•
•
the ability to guarantee a programmable maximum latency to DMA agents
the ability to guarantee a programmable amount of bandwidth to DMA agents
the ability to provide equal opportunity to DMA agents
any (complex) combination of the three mechanisms mentioned above
Time-Division Multiple Access (TDMA) arbitration to guarantee maximum latency
priority arbitration to guarantee bandwidth to reading S
DMA) agents
round-robin arbitration to guarantee bandwidth to writing SRT DMA agents
round-robin arbitration to provide equal opportunity for Best Effort (BE) DMA
agents
ID
0xB
0xC
0xD
0xE:0xF
and
Figure 3 on page 3-30
Rev. 3 — 17 March 2006
Modules
SPDI/O, AI/O,
GPIO (r,w)
DVDD
DCS Gate
Reserved
DMA
Channels
3 x R, 3 x W
1 x R, 1 x W
1 x W
for a simplified block diagram of PNX15xx
…Continued
Chapter 3 System On Chip
Buffer size
2 x 128-byte buffer
2 x 256-byte buffer
2 x 32-bit buffer
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 26: Memory Arbiter
PNX15xx Series
oft Real Time DMA (
Transaction
size
64 Bytes
128 Bytes
8 Bytes
SRT
26-3