pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 682

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
PNX15XX_SER_3
Product data sheet
Bit
Offset 0x07 2020
31:16
15
14:5
4:2
1
0
Offset 0x07 2024
31:2
1
0
Offset 0x07 2028
31:13
12:8
7:5
4:0
Offset 0x07 202C
31:16
15:0
Offset 0x07 2030
31:16
15:0
Offset 0x07 2030
31:3
2
1
Symbol
-
RESET_MII_MGMT
-
CLOCK_SELECT
SUPPRESS_
PREAMBLE
SCAN_INCREMENT
-
SCAN
READ
-
PHY_ADDRESS
-
REGISTER_ADDRESS
-
WRITE_DATA
-
READ_DATA
-
NOT_VALID
SCANNING
MII Mgmt Configuration (MCFG)
MII Mgmt Command (MCMD)
MII Mgmt Address (MADR)
MII Mgmt Write Data (MWTD)
MII Mgmt Read Data (MRDD)\
MII Mgmt Read Data (MRDD)\
…Continued
Acces
s
-
R/W
-
R/W
R/W
R/W
-
R/W
R/W
-
R/W
-
R/W
-
WO
-
RO
-
RO
RO
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 3 — 17 March 2006
Description
Unused
For more information refer to the MII Interface documentation [2].
Unused
This field is used by the clock divide logic to create the MII
Management Clock (MDC) which IEEE 802.3u defines to be no
faster than 2.5 MHz. Some PHYs support clock rates up to 12.5
MHz, however. For more information refer to the MII Interface
documentation [2].
For more information refer to the MII Interface documentation [2].
For more information refer to the MII Interface documentation [2].
Unused
This bit causes the MII Management module to perform read cycles
continuously. This is useful for monitoring the Link Fail timer, for
example.
This bit causes the MII Management module to perform a single
read cycle. The read data is returned in Register MRDD (MII Mgmt
Read Data).
Unused
This field represents the 5-bit PHY address field of Management
cycles. Up to 31 PHYs can be addressed (0 is reserved).
Unused
This field represents the 5-bit Register Address field of
Management cycles. Up to 32 registers can be accessed.
Unused
When written, an MII Management write cycle is performed using
the 16-bit data and the pre-configured PHY and Register addresses
from Register (0x0A).
Unused
Following a MII Management Read Cycle, the 16-bit data can be
read from this location.
Unused
When set, this bit indicates the MII Management Read cycle has not
completed, and the Read Data is not yet valid.
When set, this bit indicates a scan operation (continuous MII
Management Read cycles) is in progress.
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
23-13