pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 170

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.10 VDO Clocks
An interrupt is generated whenever the signal 'clock present' changes status.
Therefore an interrupt is generated if a clock changes from 'present' to 'non-present’
OR from 'non-present to 'present'. The interrupt registers are implemented using the
standard peripheral interrupt module and can thus be enabled/cleared/set by
software.
In the PNX15xx Series all of the above clocks can also be generated internally. In this
case the clock detection circuit can still be enabled. If the internal source is changed
then the clock detection circuit will detect the period of time that there is not a clock.
At this time the logic updates the interrupt status register and asserts an interrupt if
the interrupt is enabled. The interrupts are by default disabled and should remain that
way as long as the clock is generated internally. If in the course of time the output
clock is changed to an input the interrupt status register needs to be cleared before
the interrupts are enabled.
The two VDO out clocks, VDO_CLK1 and VDO_CLK2, have several operating
modes. A brief explanation of these modes is included in this section. Each clock has
three possible modes, input, separate output, and feedback mode. In input mode an
external clock is driving these clocks (hence driving QVCP/LCD and FGPO). In
separate output mode the clock module drives both the clocks going to the IP (QVCP/
LCD and FGPO) and to its related output clock VDO_CLK1 and VDO_CLK2. In this
case the source of the clock is the same, but the paths are totally separate. The third
mode is feedback mode. In feedback mode the clock module drives the output clock,
VDO_CLK1 and VDO_CLK2. This clock is then feedback through the pad to the clock
module. Then it goes on to the IP (QVCP/LCD and FGPO). Diagrams of these clocks
can be found in
To select between output and input mode a bit is provided in each of the configuration
registers for qvcp and fgpo. Writing to the qvcp_output_enable bit will change the
direction of the qvcp clock. Writing to the fgpo_output_enable bit will change the
direction of the fgpo clock. The output mode (separate or feedback) for the qvcp is
selected by the qvcp_output_select bit. The fgpo_output_select bit selects the mode
(separate or feedback) for the fgpo clock.
Both VDO clocks can also be programmed to have an inverted clock. There are two
possible ways to invert the clock. If the invert clock bit is set then the inverted clock
goes to the IP and the non inverted clock goes to the clock outputs. The qvcp clock is
inverted by setting the invert_qvcp_clock bit in the qvcp configuration register. The
fgpo clock is inverted by setting the invert_fgpo_clock bit in the fgpo configuration
register. Also in output mode the qvcp source clock can be inverted by setting the
sel_clk_qvcp bit to ‘10’. The fgpo source clock can also be inverted by setting the
sel_clk_fgpo bit to ‘10’. By doing this the clock is inverted to both the internal and
external version of the clock. In input mode the clock coming into the chip is inverted
before being sent to the IP. In qvcp this is done by again writing to the
invert_qvcp_clock bit. In fgpo the invert_fgpo_clock bit can also be set to invert the
clock to the IP. In input mode the sel_clk_qvcp does not get used.
For both clocks they come out of reset in a quasi-input/output mode. The pad is set to
be an input and the IP is being driven by the crystal clock (XTAL_IN) and not the input
clock (if any). This is to allow the IP to reset if there isn’t an input clock as well as
Figure 17 on page 5-28
Rev. 3 — 17 March 2006
and
Figure 18 on page
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
5-28.
5-19