pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 662

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 8: VLD Error Handling
PNX15XX_SER_3
Product data sheet
Cycle
No.
i
i to j
k
l
Action
VLD sets the appropriate error bit in the
VLD_MC_STAUS register
When the vld_mc_error signal is high, VLD completes
any pending control or memory hwy. transactions.
The valid data in the DMA output buffers will be flushed
to the main memory.
Then VLD asserts the vld_ready_to_reset signal and
waits for the CPU to reset.
If (vld_ready_to_reset) then the VLD interrupts the CPU. Assumes k>j; otherwise it is jth cycle. The corresponding
CPU will perform the software reset.
3.4.1 Unexpected Start Code
3.4.2 RL Overflow
3.4.3 Flush
When VLD encounters an unexpected start code, VLD sets the ‘Start Code Detected’
and ‘Bitstream Error’ flags (in VLD_MC_STATUS register). The start code value is left
in the shift register (VLD_SR). VLD interrupts the CPU, if one of the corresponding
interrupt bits in the VLD_IE register is enabled
If the VLD encounters a situation where the last data for a macroblock is being
emitted and the Run-Length code is not 0xFF, then the RL Overflow error flag is
asserted and an interrupt is generated if the corresponding interrupt enable bit is set.
.
The flush_cmd will be issued in two cases:
The CPU will set the
first case.
The flush_cmd will be issued when the VLD stops after interrupting the CPU for the
dma_input_done reason in the first case, and when the VLD stops after interrupting
the CPU for the start_code_detected reason in the second case.
1. The bitstream contains error bits for a known amount of bytes and would like to
2. when CPU decides to switch the bitstream at the start of a new slice-start-code in
terminate the decoding at a particular byte-offset of the bitstream buffer, and
a new row.
Rev. 3 — 17 March 2006
DMA_input_done_mode
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Remarks
The vld_mc_error signal is formed by OR’ing together all
of the error bits in the VLD_MC_STATUS register is the
Hence any MC error also drives the vld_mc_error signal
high and the following error handling steps still apply
Any DMA transactions, once started, will not be aborted
in the middle
interrupt enable (IE) bit in the VLD_IE register is ‘1’ for
the VLD to raise the interrupt.
Refer to
Section 3.1
bit to ‘1’ in the VLD_CTL register for the
for the software reset procedure
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
21-14