ep1s25 Altera Corporation, ep1s25 Datasheet - Page 64
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ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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TriMatrix Memory
Figure 2–27. Read/Write Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
2–50
Stratix Device Handbook, Volume 1
wraddress[ ]
address[ ]
byteena[ ]
outclken
wrclock
rdclock
inclken
All registers shown except the rden register have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
data[ ]
wren
rden
Figure
8 LAB Row
Clocks
8
2–27:
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Write Address
Byte Enable
Read Enable
Write Enable
Notes
Memory Block
(1),
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
(2)
D
ENA
Q
Altera Corporation
To MultiTrack
Interconnect
July 2005
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