ep1s25 Altera Corporation, ep1s25 Datasheet - Page 257
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ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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High-Speed I/O
Specification
Altera Corporation
January 2006
t
f
t
t
Timing unit interval (TUI)
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t
t
J
W
C
HSCLK
RISE
FALL
HSDR
DUTY
LOCK
Table 4–124. High-Speed Timing Specifications & Terminology
High-Speed Timing Specification
Table 4–124
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Maximum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges,
including t
measurement.
The period of time during which the data must be valid to be captured
correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = t
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Deserialization factor (width of internal data bus).
PLL multiplication factor.
provides high-speed timing specifications definitions.
SW
CO
(max) – t
variation and clock skew. The clock is included in the TCCS
SW
(min).
C
/w).
Terminology
Stratix Device Handbook, Volume 1
HSDR
DC & Switching Characteristics
= 1/TUI).
4–87