ep1s25 Altera Corporation, ep1s25 Datasheet - Page 240
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ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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Timing Model
4–70
Stratix Device Handbook, Volume 1
Note to
(1)
1.5-V LVTTL
GTL+
CTT
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.5-V HSTL Class I
1.8-V HSTL Class I
LVDS
LVPECL
PCML
HyperTransport
technology
LVCMOS
Table 4–106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins
Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
These parameters are only available on row I/O pins.
Parameter
Parameter
Table 4–103
12 mA
24 mA
through 4–106:
2 mA
4 mA
8 mA
2 mA
4 mA
8 mA
-5 Speed Grade
-5 Speed Grade
Min
Min
5,460
2,690
1,398
1,822
–196
–148
–147
–608
Max
Max
845
638
144
604
211
955
733
372
–93
684
233
6
1
-6 Speed Grade
-6 Speed Grade
Min
Min
5,733
2,824
1,468
1,002
1,913
–206
–156
–155
–638
Max
Max
887
670
151
634
221
769
390
–98
718
245
6
1
-7 Speed Grade
-7 Speed Grade
Min
Min
5,733
2,824
1,468
1,002
1,913
–206
–156
–155
–638
Max
Max
887
670
151
634
221
769
390
–98
718
245
6
1
-8 Speed Grade
-8 Speed Grade
Min
Min
Altera Corporation
(Part 2 of 2)
5,733
2,824
1,468
1,002
1,913
–206
–156
–155
–638
January 2006
Max
Max
887
670
151
634
221
769
390
–98
718
245
6
1
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps