ep1s25 Altera Corporation, ep1s25 Datasheet - Page 196
ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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Timing Model
4–26
Stratix Device Handbook, Volume 1
t
t
t
t
t
t
t
MRAMDATABH
MRAMADDRBSU
MRAMADDRBH
MRAMDATACO1
MRAMDATACO2
MRAMCLKHL
MRAMCLR
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
B port hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in
reported by the timing analyzer in the Quartus II software.
Minimum clear pulse width.
Parameter
Table 4–36 on page 4–20
Altera Corporation
January 2006
and as
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