ep1s25 Altera Corporation, ep1s25 Datasheet - Page 255

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
January 2006
LVDS
HyperTransport
technology
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
LVPECL
PCML
Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins
in Wire-Bond Packages (Part 2 of 2)
Table 4–123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Wire-Bond Packages (Part 1 of 2)
I/O Standard
I/O Standard
(2)
(2)
(2)
(2)
-6 Speed
-6 Speed
Grade
Grade
311
311
200
200
200
200
200
125
125
110
150
110
110
110
225
200
225
200
200
200
200
200
200
125
311
400
90
-7 Speed
-7 Speed
Grade
Grade
275
275
175
175
175
175
175
100
100
133
100
100
100
200
167
200
167
175
175
175
175
175
100
270
311
90
80
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
-8 Speed
-8 Speed
Grade
Grade
275
275
175
175
175
175
175
100
100
133
100
100
100
200
167
200
167
175
175
175
175
100
270
311
175
90
80
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
4–85