adsp-21462w Analog Devices, Inc., adsp-21462w Datasheet - Page 41

• Manufacturer Part Number: adsp-21462w
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 36. ASRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
AMI_DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SRCSFS
SRCHFS
SRCCLKW
SRCCLK
SRCTDD
SRCTDH
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
Clock Width
Clock Period
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
DAI_P20
DAI_P20
DAI_P20
(SDATA)
(SCLK)
(FS)
-
-
-
1
1
1
Figure 26. ASRC Serial Output Port Timing
Rev. PrA | Page 41 of 60 | November 2008
t
SRCTDH
t
SRCTDD
t
SRCCLKW
SAMPLE EDGE
t
SRCSFS
ADSP-21462W/ADSP-21465W/ADSP-21467
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the
drive edge.
t
SRCHFS
t
SRCCLK
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns