adsp-21462w Analog Devices, Inc., adsp-21462w Datasheet - Page 21

• Manufacturer Part Number: adsp-21462w
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
TIMING SPECIFICATIONS
The ADSP-21462W/ADSP-21465W/ADSP-21467’s internal
clock (a multiple of CLKIN) provides the clock signal for timing
internal memory, processor core, and serial ports. During reset,
program the ratio between the processor’s internal clock fre-
quency and external (CLKIN) clock frequency with the
CLKCFG1–0 pins (see
switching frequencies for the serial ports, divide down the inter-
nal clock, using the programmable divider control of each port
(DIVx for the serial ports).
Core clock frequency can be calculated as:
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency falls in
between 160 MHz and 800 MHz. The VCO frequency is calcu-
lated as follows:
where:
f
PLLM is the multiplier value programmed
f
VCO
INPUT
f
CCLK
f
VCO
RESET
is the VCO frequency
XTAL
is the input frequency to the PLL in MHz.
= (2 × PLLM × f
= 2 PLLM f
BUF
CLKIN
4096 CLKIN
DELAY OF
CYCLES
Table 9 on Page
INPUT
DIVIDER
INPUT
CLKIN
PMCTL
) (2 × PLLN)
PLLI
RESETOUT
CLK
17). To determine
Figure 3. Core Clock and System Clock Relationship to CLKIN
CLK_CFGx/PMCTL
FILTER
LOOP
Rev. PrA | Page 21 of 60 | November 2008
MULTIPLIER
CLKOUT
PLL
PLL
VCO
ADSP-21462W/ADSP-21465W/ADSP-21467
DIVIDER
PLL
Figure 3
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2136x SHARC Processor Programming Reference.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock.
f
f
Note the definitions of various clock periods shown in
which are a function of CLKIN and the appropriate ratio con-
trol shown in
Table 11. CLKOUT and CCLK Clock Generation Operation
INPUT
INPUT
Timing
Requirements
CLKIN
CCLK
= CLKIN when the input divider is disabled
= CLKIN 2 when the input divider is enabled
CLK_CFGx/
PMCTL
shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
PMCTL
Table
CCLK
11.
BUF
Description
Input Clock
Core Clock
DIVIDER
MLB CLOCK
PMCTL
DIVIDE
LINKPORT
DDR2
BY 2
PMCTL
DIVIDER
DIVIDER
CLOCK
PMCTL
PCLK
RESETOUT/
CORERST
CLKOUT
CLK_CFGx/
PMCTL
CLK_CFGx/
Calculation
1/t
1/t
CLK_CFGx/
PMCTL
PMCTL
CK
CCLK
PCLK
CCLK
MLBSYSCLK
DDR2_CLK
LCLK
Table 12