adsp-21462w Analog Devices, Inc., adsp-21462w Datasheet - Page 13

• Manufacturer Part Number: adsp-21462w
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of
A = asynchronous, I = input, O = output, S = synchronous,
(A/D) = active drive, (O/D) = open drain, and T = three-state,
(pd) = pull-down resistor, (pu) = pull-up resistor.
Table 6. Pin List
Name
AMI_ADDR
AMI_DATA
DAI _P
DPI _P
AMI_ACK
AMI_RD
AMI_WR
DDR2_ADDR
DDR2_BA
14–1
20–1
2-0
7–0
23–0
15–0
Type
I/O/T
I/O/T
I/O with fixed weak
pull-up on input
path
I/O with fixed weak
pull-up only on
input path
I (pu)
O/T
O/T
O/T
O/T
1, 2
1, 2
LVTTL SSTL18
Rev. PrA | Page 13 of 60 | November 2008
Table
State
During
and After
Reset
High-Z/
driven low
(boot)
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z/
Driven low
High-Z/
Driven low
6:
ADSP-21462W/ADSP-21465W/ADSP-21467
Description
External Address. The ADSP-21462W/ADSP-21465W/ADSP-21467 outputs
addresses for external memory and peripherals on these pins. The data pins
can be multiplexed to support the PDAP (I) and PWM (O). After reset, all
AMI_ADDR
mode (default). When configured in the IDP_PDAP_CTL register, IDP
channel 0 scans the AMI_ADDR
External Data. The data pins can be multiplexed to support the external
memory interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset,
all AMI_DATA pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS mode
(default).
Digital Applications Interface Pins. These pins provide the physical
interface to the DAI SRU. The DAI SRU configuration registers define the com-
bination of on-chip audiocentric peripheral inputs or outputs connected to
the pin and to the pin’s output enable. The configuration registers of these
peripherals then determine the exact behavior of the pin. Any input or output
signal present in the DAI SRU may be routed to any of these pins. The DAI SRU
provides the connection from the serial ports, the S/PDIF module, input data
ports (2), and the precision clock generators (4), to the DAI_P20–1 pins.
Digital Peripheral Interface. These pins provide the physical interface to the
DPI SRU. The DPI SRU configuration registers define the combination of on-
chip peripheral inputs or outputs connected to the pin and to the pin’s output
enable. The configuration registers of these peripherals then determines the
exact behavior of the pin. Any input or output signal present in the DPI SRU
may be routed to any of these pins. The DPI SRU provides the connection from
the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to the
DPI_P14–1 pins.
Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK
(low) to add wait states to an external memory access. AMI_ACK is used by I/O
devices, memory controllers, or other peripherals to hold off completion of
an external memory access.
AMI Port Read Enable. AMI_RD is asserted whenever the ADSP-
21462W/ADSP-21465W/ADSP-21467 reads a word from external memory.
AMI_RD has fixed internal pull-up resistor
External Port Write Enable. AMI_WR is asserted when the ADSP-
21462W/ADSP-21465W/ADSP-21467 writes a word to external memory.
AMI_WR has fixed internal pull-up resistor
DDR2 Address pins. DDR2 address pins.
DDR2 Bank Address Input pins. Define which bank an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. BA2–0
define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
23-0
pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS
23–0
pins for parallel input data.
1, 2
1, 2
.
.