adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 6

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21161N
PM bus, with one dedicated to each memory block, assures
single-cycle execution with two data transfers. In this case, the
instruction must be available in the cache.
Off-Chip Memory and Peripherals Interface
The ADSP-21161N’s external port provides the processor’s
interface to off-chip memory and peripherals. The 62.7-M word
off-chip address space (254.7-M word if all SDRAM) is included
in the ADSP-21161N’s unified address space. The separate on-
chip buses—for PM addresses, PM data, DM addresses, DM
data, I/O addresses, and I/O data—are multiplexed at the external
port to create an external system bus with a single 24-bit address
bus and a single 32-bit data bus. Every access to external memory
is based on an address that fetches a 32-bit word. When fetching
an instruction from external memory, two 32-bit data locations
are being accessed for packed instructions. Unused link port lines
can also be used as additional data lines DATA15
allowing single-cycle execution of instructions from external
memory, at up to 100 MHz.
alignment of various accesses to external memory.
INTERNAL
MEMORY
SPACE
MULTIPROCESSOR
MEMORY
SPACE
IOP REGISTERS OF ADSP-21161N
IOP REGISTERS OF ADSP-21161N
IOP REGISTERS OF ADSP-21161N
IOP REGISTERS OF ADSP-21161N
IOP REGISTERS OF ADSP-21161N
IOP REGISTERS OF ADSP-21161N
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
LONG WORD ADDRESSING
Figure 3 on Page 7
IOP REGISTERS
WITH ID = 001
WITH ID = 010
WITH ID = 011
WITH ID = 100
WITH ID = 101
WITH ID = 110
RESERVED
shows the
– DATA0,
Figure 2. Memory Map
ADDRESS
0x0000 0000 - 0x0001 FFFF
0x0002 0000 - 0x0002 1FFF (BLK 0)
0x0002 8000 - 0x0002 9FFF (BLK 1)
0x0004 0000 - 0x0004 3FFF (BLK 0)
0x0005 0000 - 0x0005 3FFF (BLK 1)
0x0008 0000 - 0x0008 7FFF (BLK 0)
0x000A 0000 - 0x000A 7FFF (BLK 1)
0x0010 0000 - 0x0011 FFFF
0x0012 0000 - 0x0013 FFFF
0x0014 0000 - 0x0015 FFFF
0x0016 0000 - 0x0017 FFFF
0x0018 0000 - 0x0019 FFFF
0x001A 0000 - 0x001B FFFF
0x001C 0000
0x001F FFFF
EXTERNAL MEMORY SPACE
–6–
The external port supports asynchronous, synchronous, and syn-
chronous burst accesses. Synchronous burst SRAM can be
interfaced gluelessly. The ADSP-21161N also can interface glue-
lessly to SDRAM. Addressing of external memory devices is
facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. The ADSP-21161N
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to memory
and peripherals with variable access, hold, and disable time
requirements.
SDRAM Interface
The SDRAM interface enables the ADSP-21161N to transfer
data to and from synchronous DRAM (SDRAM) at the core
clock frequency or at one-half the core clock frequency. The
NOTE: BANK SIZES ARE FIXED
BANK 0
BANK 1
BANK 2
BANK 3
0x08FF FFFF (NON-SDRAM)
0x0CFF FFFF (NON-SDRAM)
0x0FFF FFFF (SDRAM)
ADDRESS
0x0020 0000
0x00FF FFFF (NON-SDRAM)
0x03FF FFFF (SDRAM)
0x0400 0000
0x04FF FFFF (NON-SDRAM)
0x07FF FFFF (SDRAM)
0x0800 0000
0x0BFF FFFF (SDRAM)
0x0C00 0000
MS0
MS1
MS2
MS3
REV. A