adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 41

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew that
can be introduced in the transmission path between LDATA and
LCLK. Setup skew is the maximum delay that can be introduced
in LDATA relative to LCLK, (setup skew = t
– t
in LCLK relative to LDATA, (hold skew = t
– t
Table 27. Link Ports
1
REV. A
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
LACK goes low with t
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLALC
SLDCL
HLDCL
). Hold skew is the maximum delay that can be introduced
). Calculations made directly from speed specifications
LDAT7-0
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period
LCLK Width Low
LCLK Width High
LACK Low Delay After LCLK High
LACK (OUT)
LCLK
DLALC
RECEIVE
–
Receive
relative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.
LCLKTWL
LCLKTWH
t
LCLKRWH
Figure 30. Link Ports—Receive
min – t
min– t
t
SLDCL
1
DLDCH
HLDCH
IN
–41–
t
LCLKIW
will result in unrealistically small skew times because they include
multiple tester guardbands. The setup and hold skew times
shown below are calculated to include only one tester guardband.
ADSP-21161N Setup Skew = 1.5 ns max
ADSP-21161N Hold Skew = 1.5 ns max
Note that there is a two-cycle effect latency between the link port
enable instruction and the DSP enabling the link port.
t
HLDCL
t
LCLKRWL
Min
1
3.5
t
4.0
4.0
8
LCLK
t
DLALC
Max
12
ADSP-21161N
Unit
ns
ns
ns
ns
ns
ns