adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 4

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21161N
The ADSP-21161N continues SHARC’s industry-leading
standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include a 1 M bit dual ported SRAM memory, host
processor interface, I/O processor that supports 14 DMA
channels, four serial ports, two link ports, SDRAM controller,
SPI interface, external parallel bus, and glueless multiprocessing.
The block diagram of the ADSP-21161N
the following architectural features:
Two processing elements, each made up of an ALU, Mul-
tiplier, Shifter, and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle
Interval timer
(HOST OR SLAVE)
COMPATIBLE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICES
CLOCK
(2 MAX)
SERIAL
DEVICE
SPI
DEVICE
SERIAL
SERIAL
DEVICE
SERIAL
DEVICE
LINK
12
3
2
MOSI
MISO
LBOOT
RPBA
LXCLK
LXDAT7-0
D0A
D0B
D1A
D1B
D2A
D2B
D3A
D3B
SPICLK
SPIDS
RESET
CLKIN
XTAL
CLK_CFG1-0
EBOOT
IRQ2-0
FLAG11-0
TIMEXP
ID2-0
LXACK
SCLK0
FS0
SCLK1
FS1
SCLK2
FS2
SCLK3
FS3
CLKDBL
ADSP-21161N
on Page 1
RSTOUT
DATA47-16
ADDR23-0
SDCLK1-0
DMAG2-1
DMAR2-1
CLKOUT
Figure 1. System Diagram
SDCKE
SDA10
illustrates
MS3-0
SDWE
BR6-1
BRST
REDY
SBTS
JTAG
DQM
HBG
BMS
ACK
RAS
CAS
HBR
WR
RD
CS
PA
7
–4–
Figure 1
ing system appears in
On-Chip SRAM (1 M bit)
SDRAM Controller for glueless interface to SDRAMs
External port that supports:
DMA controller
Four serial ports
Two link ports
SPI compatible interface
JTAG test access port
12 General-Purpose I/O Pins
Interfacing to off-chip memory peripherals
Glueless multiprocessing support for six ADSP-
21161N SHARCs
Host port read/write of IOP registers
shows a typical single-processor system. A multiprocess-
DATA
DATA
OE
WE
ACK
DATA
DATA
CS
ADDR
CS
ADDR
ADDR
PERIPHERALS
(OPTIONAL)
DMA DEVICE
PROCESSOR
(OPTIONAL)
(OPTIONAL)
INTERFACE
(OPTIONAL)
MEMORY
EPROM
AND
HOST
BOOT
Figure 4 on Page
RAS
CAS
DQM
CLK
CKE
CS
ADDR
DATA
WE
A10
(OPTIONAL)
SDRAM
8.
REV. A