adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 2

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21161N
KEY FEATURES (continued)
1 M Bit On-Chip Dual-Ported SRAM (0.5 M Bit Block 0,
200 Million Fixed-Point MACs Sustained Performance
Dual Data Address Generators (DAGs) with Modulo and
Zero-Overhead Looping with Single-Cycle Loop Setup,
IEEE 1149.1 JTAG Standard Test Access Port and On-Chip
Single Instruction Multiple Data (SIMD) Architecture
Parallelism in Buses and Computational Units Enables:
DMA Controller Supports:
32-Bit (or up to 48-Bit) Wide Synchronous External Port
0.5 M Bit Block 1) for Independent Access by Core
Processor and DMA
Bit-Reverse Addressing
Providing Efficient Program Sequencing
Emulation
Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Code Compatibility—At Assembly Level, Uses the
Single-Cycle Execution (with or without SIMD) of: a
Transfers Between Memory and Core at Up to Four
Accelerated FFT Butterfly Computation through a
14 Zero-Overhead DMA Channels for Transfers between
64-Bit Background DMA Transfers at Core Clock Speed,
800 M Bytes/s Transfer Rate over IOP Bus
Host Processor Interface to 8-, 16-, and 32-Bit
Provides:
Glueless Connection to Asynchronous, SBSRAM and
Memory Interface Supports Programmable Wait State
Up to 50 MHz Operation for Non-SDRAM Accesses
1:2, 1:3, 1:4, 1:6, 1:8 Clock into Core Clock Frequency
24-Bit Address, 32-Bit Data Bus. 16 Additional Data
Direct Reads and Writes of IOP Registers from Host or
62.7 Mega-Word Address Range for Off-Chip SRAM and
Executes the Same Instruction, but Operates on
Different Data
Same Instruction Set as Other SHARC DSPs
Multiply Operation, an ALU Operation, a Dual
Memory Read or Write, and an Instruction Fetch
32-Bit Floating- or Fixed-Point Words Per Cycle,
Sustained 1.6 Gbytes/s Bandwidth
Multiply with Add and Subtract
ADSP-21161N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports,
Link Ports, or Serial Peripheral Interface (SPI-
Compatible)
in Parallel with Full-Speed Processor Execution
Microprocessors; the Host Can Directly Read/Write
ADSP-21161N IOP Registers
SDRAM External Memories
Generation and Wait Mode for Off-Chip Memory
Multiply Ratios
Lines via Multiplexed Link Port Data Pins Allow
Complete 48-Bit Wide Data Bus for Single-Cycle
External Instruction Execution
Other 21161N DSPs
SBSRAM Memories
–2–
SDRAM Controller for Glueless Interface to Low Cost
Multiprocessing Support Provides:
Serial Ports Provide:
Serial Peripheral Interface (SPI)
12 Programmable I/O Pins
1 Programmable Timer
32-48, 16-48, 8-48 Execution Packing for Executing
32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, Data
Can be Configured to have 48-Bit Wide External Data
External Memory
Zero Wait State, 100 MHz Operation for Most Accesses
Extended External Memory Banks (64 M Words) for
Page Sizes up to 2048 Words
An SDRAM Controller Supports SDRAM in Any and All
Support for Interface to Run at Core Clock and Half the
Support for 16 M Bits, 64 M Bits, 128 M Bits, and
254 Mega-Word Address Range for Off-Chip SDRAM
Glueless Connection for Scalable DSP Multiprocessing
Distributed On-Chip Bus Arbitration for Parallel Bus
Two 8-Bit Wide Link Ports for Point-to-Point
400 M Bytes/s Transfer Rate over Parallel Bus
200 M Bytes/s Transfer Rate Over Link Ports
Four 50 M Bit/s Synchronous Serial Ports with
8 Bidirectional Serial Data Pins, Configurable as Either a
I
128 Channel TDM Support for T1 and E1 Interfaces
Companding Selection on a Per Channel Basis in TDM
Slave Serial Boot through SPI from a Master SPI Device
Full-Duplex Operation
Master-Slave Mode Multimaster Support
Open-Drain Outputs
Programmable Baud Rates, Clock Polarities and Phases
2
S Support, Programmable Direction for 8
Instruction Directly from 32-Bit, 16-Bit, or 8-Bit Wide
External Memories
Packing for DMA Transfers Directly from 32-Bit,
16-Bit, or 8-Bit Wide External Memories to and from
Internal 32-, 48-, or 64-Bit Internal Memory
Bus, if Link Ports are not Used. The Link Port Data
Lines are Multiplexed with the Data Lines D0 to D15
and are Enabled through Control Bits in SYSCON
SDRAM Accesses
Memory Banks
Core Clock Frequency
256 M Bits with SDRAM Data Bus Configurations of
Memory
Architecture
Connect of Up to Six ADSP-21161Ns, Global Memory,
and a Host
Connectivity Between ADSP-21161Ns
Companding Hardware
Transmitter or Receiver
Simultaneous Receive and Transmit Channels, or Up
to Either 16 Transmit Channels or 16 Receive
Channels
Mode
4,
8,
16, and
32
REV. A