adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 45

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

SPI Interface—Slave
Table 42. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSDHI
DDSPIDS
HDSPIDS
DSOV
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(CP = 1)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(INPUT)
MISO
(INPUT)
MISO
(INPUT)
(INPUT)
SPIDS
MOSI
MOSI
t
S D S C O
t
t
t
D S O E
D S O V
D S O E
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
t
t
S P I C H S
S S P I D S
t
t
D D S P I D S
MSB VALID
S P I C L S
MSB
MSB VALID
MSB
t
D D S P I D S
Rev. A | Page 45 of 56 | August 2006
t
t
S P I C H S
S P I C L S
Figure 35. SPI Slave Timing
t
S S P I D S
t
D D S P I D S
LSB VALID
ADSP-21367/ADSP-21368/ADSP-21369
t
t
S P I C L K S
S S P I D S
t
H D S P ID S
LSB
LSB VALID
t
H S P ID S
t
t
H S P ID S
H D S
LSB
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
2 × t
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
t
S D P P W
– 2
– 2
– 2
t
t
t
D S D H I
H D S P ID S
D S D H I
Max
6.8
6.8
9.5
5 × t
PCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns