adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 37

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

Input Data Port
The timing requirements for the IDP are given in
signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 33. IDP
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20
DAI_P20
DAI_P20
(SDATA)
(SCLK)
(FS)
-
-
-
1
1
1
Table
Rev. A | Page 37 of 56 | August 2006
Figure 24. IDP Master Timing
33. IDP
t
IDPCLKW
t
SISFS
t
SISD
SAMPLE EDGE
t
IDPCLK
ADSP-21367/ADSP-21368/ADSP-21369
t
SIHFS
t
SIHD
Min
3.8
2.5
2.5
9
24
2.5
Max
Unit
ns
ns
ns
ns
ns
ns