adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 35

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

Table 31. Serial Ports—Enable and Three-State
1
Table 32. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Referenced to drive edge.
Parameter
Switching Characteristics
t
t
The t
This figure reflects changes made to support left-justified sample pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
1
1
1
1
1
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or External Receive
FS with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20
DAI_P20
DAI_P20
DAI_P20
NOTE: SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20
DAI_P20
DAI_P20
(SCLK)
(SCLK)
(FS)
(FS)
-
-
-
-
-
-
1
1
1
1
1
1
DRIVE
DRIVE
t
DDTLFSE
t
DDTLFSE
Figure 22. External Late Frame Sync
Rev. A | Page 35 of 56 | August 2006
t
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
SFSE/I
SFSE/I
t
LATE EXTERNAL TRANSMIT FS
DDTENFS
t
DDTENFS
SAMPLE
SAMPLE
1ST BIT
DATA CHANNEL
1ST BIT
t
HDTE/I
t
HDTE/I
ADSP-21367/ADSP-21368/ADSP-21369
DRIVE
DRIVE
t
A/B) ARE ROUTED TO THE DAI_P20
HFSE/I
t
HFSE/I
1
t
DDTE/I
Min
2
–1
t
Min
0.5
DDTE/I
2ND BIT
2ND BIT
-
-
1 PINS.
1 PINS
Max
10
Max
7.75
Unit
ns
ns
ns
Unit
ns
ns