adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 23

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adsp-21367kbpz-2a

Manufacturer Part Number
adsp-21367kbpz-2a
Description
Sharc Processors
Manufacturer
Analog Devices, Inc.
Datasheet
Reset
Table 15. Reset
1
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 16. Interrupts
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is low, assuming stable
Parameter
Timing Requirement
t
WRST
SRST
V
IPW
DD
1
and CLKIN (not including startup time of external clock oscillator).
IRQx Pulse Width
RESET Pulse Width Low
RESET Setup Before CLKIN Low
RESET
CLKIN
DAI_P20 - 1
DPI_14 - 1
FLAG2 - 0
(IRQ2 - 0)
Rev. A | Page 23 of 56 | August 2006
Figure 9. Interrupts
Figure 8. Reset
t
WRST
t
IPW
Min
4t
8
ADSP-21367/ADSP-21368/ADSP-21369
CK
Min
2 × t
PCLK
+2
t
SRST
Max
Max
Unit
ns
Unit
ns
ns

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