adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 31

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 26. Memory Write—Bus Master
1
2
3
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) x t
ACK Delay/Setup: System must meet t
The falling edge of MSx is referenced.
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
WWR
DDWR
WDE
ADDRESS
MSx
DATA
ACK
WR
RD
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulse Width
Data Setup Before WR High
Address Hold After WR Deasserted
Data Hold After WR Deasserted
WR High to WR, RD Low
Data Disable Before RD Low
WR Low to Data Enabled
DAAK
t
t
DAWL
DAAK
t
, or t
WDE
DSAK
1, 3
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
2
t
DSAK
Figure 19. Memory Write—Bus Master
1, 2
Rev. A | Page 31 of 56 | August 2006
2
t
DAWH
SDCLK
SDCLK
.
.
t
Min
t
t
W – 1.3
t
H + 0.15
H + 0.02
t
2t
t
WW
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
t
DDWH
– 3.1+ W
– 3.0+ W
– 1.5+ H
– 3.5
– 2.7
ADSP-21367/ADSP-21368/ADSP-21369
– 4.11
Max
t
W – 4.9
SDCLK
– 9.7 + W
t
DWHD
t
t
t
WWR
DWHA
DDWR
DAAK
or t
DSAK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.