dac1008d650 NXP Semiconductors, dac1008d650 Datasheet - Page 47

• Manufacturer Part Number: dac1008d650
• Description: Dac1008d650 Dual 10-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 48.
Default settings are shown highlighted.
Table 49.
Default settings are shown highlighted.
Table 50.
Default settings are shown highlighted.
DAC1008D650
Product data sheet
Bit
7 to 6
5
4
3
2
1
0
Bit
7 to 0
Bit
7 to 0
Symbol
MDS_EQCHECK[1:0]
MDS_RUN
MDS_NCO
MDS_SEL_LN23
MDS_32T_ENA
MDS_MASTER
MDS_ENA
Symbol
MDS_WIN_PERIOD_A[7:0]
Symbol
MDS_WIN_PERIOD_B[7:0]
10.15.2.4 Page 1 bit definition detailed description
MDS_MAIN register (address 00h) bit description
MDS_WIN_PERIOD_A register (address 01h) bit description
MDS_WIN_PERIOD_B register (address 02h) bit description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 47
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 December 2010
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
Access
R/W
for a register overview and their default values. In the following
Value
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
Value
80h
Value
40h
2×, 4× or 8× interpolating DAC with JESD204A
Description
lock mode
evaluation restart
NCO synchronization
synchronization reference
maximum delay
MDS function
Description
determines MDS window LOW-time
Description
determines MDS window HIGH-time
MDS mode
lock when (early = 1 and late = 1)
lock when (early = 1 and late = 1 and equal = 1)
lock when equal = 1
force_lock (equal-check = 1)
no action
transition from 0 to 1 restarts evaluation_counter
no action
NCO synchronization enabled
use lane 1 enable as reference for
synchronization
use lane 2/lane 3 enable as reference for
synchronization
maximum coarse delay is 16T_dclk
maximum coarse delay is 32T_dclk
slave mode
master mode
disable MDS function
enable MDS function
DAC1008D650
© NXP B.V. 2010. All rights reserved.
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