dac1008d650 NXP Semiconductors, dac1008d650 Datasheet - Page 18

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dac1008d650

Manufacturer Part Number
dac1008d650
Description
Dac1008d650 Dual 10-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
DAC1008D650
Product data sheet
The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges will reach each of the
DACs at different times.
The worst case clock skew is given by δt
sum of the trace delay and the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by Δt = TDAC − δt
Fig 9.
Clock skew case 1: Master is the farthest
slave 1 clock
slave 2 clock
master clock
All information provided in this document is subject to legal disclaimers.
ref clock
Rev. 2 — 17 December 2010
PH03
PH02
PH01
2×, 4× or 8× interpolating DAC with JESD204A
1
= PH01 − PH03, where PH0x represents the
TDAC
DAC1008D650
001aal072
© NXP B.V. 2010. All rights reserved.
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