adv7152 Analog Devices, Inc., adv7152 Datasheet - Page 4

• Manufacturer Part Number: adv7152
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

NOTES
1
2
3
4
5
6
7
8
9
Specifications subject to change without notice.
ADV7152
TTL input values are 0 to 3 volts, with input rise/fall times
V
puts. Analog output load
SYNCOUT
Temperature range (T
Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B]; GREEN [A, B]; BLUE [A, B], Palette Selects: PS0 [A, B]; PS1 [A, B]; Pixel Controls:
SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT.
plexing, = CLOCK
These fixed values for Pipeline Delay are valid under conditions where t
line Delay is increased by 2 clock cycles for 2:1 mode after calibration cycle is performed.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the
10% and 90% points of full-scale transition. Settling time measured from the 50% point of full-scale transition to the output remaining within
does not include clock and data feedthrough.)
t
t
lated back to remove the effects of charging the 100 pF capacitor. This means that the time, t
and as such is independent of external databus loading capacitances.
23
25
5% for all versions.
is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing;
AA
and t
is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
–0.8 V to V
24
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
30 pF.
AA
–1.8 V, with input rise/fall times
MIN
PIXEL INPUT
(1:1 MULTIPLEXING)
(2:1 MULTIPLEXING)
2 = 2
to T
LOADIN
10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, I
DATA*
MAX
t
1
LOADOUT
LOADOUT
ns.
): 0 C to +70 C; T
CLOCK
CLOCK
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 1. Load Circuit for Databus Access and Relinquish Times
t
Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK )
8
VALID
DATA
t
9
2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
t
4
J
(Silicon Junction Temperature)
Figure 3. LOADIN vs. Pixel Input Data
OUTPUT
3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are
t
PIN
5
TO
t
1
100pF
10
and –t
VALID
DATA
t
–4–
2
11
are met. If either t
t
3
t
6
100 C.
I
I
SINK
SOURCE
25
, quoted in the Timing Characteristics is the true value for the device
10
+2.1V
t
or –t
7
11
VALID
DATA
are not met, the part will operate but the Pipe-
= CLOCK = t
1
ns; 2:1 multi-
1 LSB. (Settling time
PLL
and
REV. B