adv7152 Analog Devices, Inc., adv7152 Datasheet - Page 29

• Manufacturer Part Number: adv7152
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

Example 2
Color Mode
Multiplexing
Databus
RAM-DAC Resolution 10-Bit
SYNC
Pedestal
Calibration
Register Initialization
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Color Palette RAM Initialization
Write
Write
Write
Write
Write
Write
Write
•
•
Write
Write
Write
**These four command lines reset the ADV7152 The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” in-
**Data for a gamma curve characteristic is obtainable in Appendix 3.
REGISTER DIAGNOSTIC TESTING
The previous examples show the register initialization sequence
for the ADV7152. These show control data going to the regis-
ters and palette RAM. As well as this writing function, it may
also be necessary, due to system diagnostic requirements, to
confirm that correct data has been transferred to each register
and palette RAM location. There are two ways to incorporate
register value/RAM value checking:
1. READ after each WRITE: After data is written to a particular
C1 C0
0
1
1
0
1
1
REV. B
put. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed
by a “1” followed by a “0” to Mode Register MR15.
register, it can be read back immediately. The following table
shows an example with Command Registers CR2 and CR3.
0
0
0
0
0
0
0FH to Mode Register (MR1)
0EH to Mode Register (MR1)
0FH to Mode Register (MR1)
2FH to Mode Register (MR1)
0FH to Mode Register (MR1)
04H to Address Register (A7–A0)
FFH to Pixel Mask Register
05H to Address Register (A7–A0)
01H to Command Reg 1 (CR1)
06H to Address Register (A7–A0)
E0H to Command Reg 2 (CR2)
07H to Address Register (A7–A0)
41H to Command Reg 3 (CR3)
00H to Address Register (A7–A0)
000H (Red Data) to RAM Location (00H)
000H (Green Data) to RAM Location (00H)
000H (Blue Data) to RAM Location (00H)
xxxH (Red Data) to RAM Location (01H)
xxxH (Green Data) to RAM Location (01H)
xxxH (Blue Data) to RAM Location (01H)
3FFH (Red Data) to RAM Location (FFH)
3FFH (Green Data) to RAM Location (FFH)
3FFH (Blue Data) to RAM Location (FFH)
R/W
0
0
1
0
0
1
•
•
D0–D7
06H
E0H
E0H
07H
40H
40H
•
•
24-Bit Gamma Corrected True Color (30 Bits)
2:1
10-Bit
Ignored
0 IRE
Every Vertical Sync
Comment
Select Command Register 2 (CR2)
Sets 24-Bit True-Color
Command Reg 2 Value Read-Back
Select Command Register 3 (CR3)
Set 2:1 Mux Mode
Command Reg 3 Value Read-Back
•
•
•
•
C1
1
1
1
1
1
0
1
0
0
0
1
0
1
C1
0
0
0
0
0
0
•
•
0
0
0
0
–29–
C0
1
1
1
1
1
0
0
0
0
0
0
0
0
C0
0
1
1
1
1
1
1
•
•
1
1
1
2. READ after all WRITEs completed: All registers and the
C1 C0
0
1
0
1
0
1
0
1
1
It is clear that this latter case requires more command lines
than the previous READ after each WRITE case.
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
•
•
0
0
0
color palette RAM are written to and set. Once this is
complete, all registers are again accessed but this time in
Read-Only mode. The table below shows this method for
Command Registers CR2 and CR3.
0
0
0
0
0
0
0
0
0
Comment
Resets to Normal Operation, 10-Bit Bus/RAM-DAC
*(Initializes Pipelining
*( “
*(Calibrates LOADOUT/LOADIN Timing
*(
Address Reg Points to Pixel Mask Register
Sets the Pixel Mask to All “1s”
Address Reg Points to Command Register 1 (CR1)
Calibrates Every Vertical Sync
Address Reg Points to Command Register 2 (CR2)
Sets 24-Bit Color, 0 IRE, No SYNC
Address Reg Points to Command Register 3 (CR3)
Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/8
Comment
Points to Color Palette RAM
(Initializes Palette RAM
(
(
(
(
(
(
(
(
(
(RAM Initialization Complete
R/W
0
0
0
0
0
1
0
1
1
to a “Gamma” Ramp**
“
D0–D7 Comment
06H
E0H
07H
40H
06H
E0H
07H
40H
40H
Sets 24-Bit True-Color
Select Command Register 3 (CR3)
Set 2:1 Mux Mode
Select CR2
CR2 Value Read-Back
Select CR3
CR3 Value Read-Back
CR3 Value Read-Back
Select Command Register 2 (CR2)
ADV7152