adv7152 Analog Devices, Inc., adv7152 Datasheet - Page 16

• Manufacturer Part Number: adv7152
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

ADV7152
Data is read from the color palette by first writing to the address
register of the color palette location to be read. The MPU per-
forms three successive read cycles from each of the red, green
and blue locations (10-bit or 8-bit) of the RAM. An internal
pointer moves from red to green to blue after each read is com-
pleted. This pointer is reset to red after a blue read or whenever
the address register is written. The address register then auto-
matically increments to point to the next RAM location, and a
similar red, green and blue palette read sequence is performed.
The address register resets to 00H following a blue read cycle of
color palette RAM location FFH.
R/W
0
0
0
0
0
0
1
1
1
1
1
1
DB = Data Bit.
C1
1
0
1
0
0
0
1
0
1
0
0
0
REGISTER
ADDRESS
(A7–A0)
07H
08H
09H
0AH
0BH
00H
01H
02H
03H
04H
05H
06H
C0
1
0
0
1
1
1
1
0
0
1
1
1
COMMAND REGISTER 1
COMMAND REGISTER 2
SYNC, BLANK & I
TEST REGISTER
ID REGISTER (READ ONLY)
COMMAND REGISTER 3
RESERVED
RESERVED
RESERVED
REVISION REGISTER
PIXEL MASK REGISTER
PIXEL TEST REGISTER
DAC TEST REGISTER
C1 = 1
C0 = 0
Databus (D9–D0)
DB7–DB0
DB7–DB0
DB7–DB0
DB9–DB0
DB9–DB0
DB9–DB0
DB7–DB0
DB7–DB0
DB7–DB0
DB9–DB0
DB9–DB0
DB9–DB0
R
R
REGISTERS
CONTROL
Figure 26. Internal Register Configuration and Address Decoding
*
*
*
*
G
G
(READ ONLY)
(READ ONLY)
(READ ONLY)
THIS REGISTER IS READ ONLY.
PLL
Table III. Interface Truth Table (10-Bit Databus Mode)
B
B
Operation
Write to Mode Register
Write to Address Register
Write to Control Registers
(Particular Control Register Determined by Address Register)
Write to RED Register
Write to GREEN Register
Write to BLUE Register
Write RGB Data to RAM Location Pointed to by Address Register (A7–A0)
Address Register = Address Register + 1
Read Mode Register
Read Address Register
Read Control Registers
(Particular Control Register Determined by Address Register)
Read RED RAM Location
Read GREEN RAM Location
Read BLUE RAM Location
(RAM Location Pointed to by Address Reg (A7–A0))
Address Register = Address Register + 1
ADDRESS REGISTER
MODE REGISTER
(MR17–MR10)
(A7–A0)
–16–
ADDRESS REG (A7–A0)
POINTS TO LOCATION
CORRESPONDING TO
Register Accesses
The MPU can write to or read from all of the ADV7152s regis-
ters. C0 and C1 determine whether the Mode Register or Ad-
dress Register is being accessed. Access to these registers is
direct. The Control Registers are accessed indirectly. The
Address Register must point to the desired Control Register.
Figure 28 along with the 8-bit and 10-bit Interface Truth Tables
illustrate the structure and protocol for device communication
over the MPU port.
C1 = 1
C0 = 1
C1 = 0
C0 = 0
REGISTER
(R9–R0)
RED
LOOK-UP TABLE RAM
REGISTER
(256 x 30)
(G9–G0)
GREEN
C1 = 0
C0 = 1
Result
DB7–DB0
DB7–DB0
DB7–DB0
DB9–DB0
DB9–DB0
DB9–DB0
MR17–MR10
A7–A0
Register Data
R9–R0
G9–G0
B9–B0
REGISTER
(B9–B0)
BLUE
ADDRESS REG =
ADDRESS REG + 1
DB7–DB0
DB9–DB0
DB9–DB0
DB9–DB0
A7–A0
MR17–MR10
Control Register
R9–R0
G9–G0
B9–B0
DB7–DB0
DB7–DB0
REV. B