adv7152 Analog Devices, Inc., adv7152 Datasheet - Page 28

• Manufacturer Part Number: adv7152
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

ADV7152
Example 1
Color Mode
Multiplexing
Databus
RAM-DAC Resolution
SYNC
Pedestal
Register Initialization
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Color Palette RAM Initialization
Write
Write
Write
Write
Write
Write
Write
•
•
Write
Write
Write
**These four command lines reset the ADV7152. The pipelines for each of the Red, Creen and Blue pixel inputs are synchronously reset to the Multiplexer’s
**This sequence of instructions would, of course, normally be coded using some form of loop instruction.
ADV7152 Initialization
After power has been supplied, the ADV7152 must be initial-
ized. The Mode Register and Control Registers must be set.
The values written to the various registers will be determined by
the desired operating mode of the part, i.e., True Color/Pseudo
Color, 2:1 Muxing/2:1 Muxing, etc.
“A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0”
followed by a “1” followed by a “0” to Mode Register MR15.
09H to Mode Register (MR1)
08H to Mode Register (MR1)
09H to Mode Register (MR1)
29H to Mode Register (MR1)
09H to Mode Register (MR1)
04H to Address Register (A7–A0)
FFH to Pixel Mask Register
05H to Address Register (A7–A0)
00H to Command Reg 1 (CR1)
06H to Address Register (A7–A0)
ECH to Command Reg 2 (CR2)
07H to Address Register (A7–A0)
40H to Command Reg 3 (CR3)
00H to Address Register (A7–A0)
00H (Red Data) to RAM Location (00H)
00H (Green Data) to RAM Location (00H)
00H (Blue Data) to RAM Location (00H)
01H (Red Data) to RAM Location (01H)
01H (Green Data) to RAM Location (01H)
01H (Blue Data) to RAM Location (01H)
FFH (Red Data) to RAM Location (FFH)
FFH (Green Data) to RAM Location (FFH)
FFH (Blue Data) to RAM Location (FFH)
•
•
•
•
24-Bit True Color
2:1
8-Bit
8-Bit
Enabled on IOG
7.5 IRE
•
•
INITIALIZATION AND PROGRAMMING
•
•
APPENDIX 5
C1
1
1
1
1
0
1
0
1
0
1
0
1
C1
0
0
0
0
0
0
•
•
0
0
0
1
0
–28–
C0
1
1
1
1
1
0
0
0
0
0
0
0
0
C0
0
1
1
1
1
1
1
•
•
1
1
1
The following section gives examples of initialization of the
ADV7152 operating in various modes.
0
R/W
0
0
0
0
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
•
•
0
0
0
Comment
Resets to Normal Operation, 8-Bit Bus/RAM-DAC
*(Initializes Pipelining
*( “
*(Calibrates LOADOUT/LOADIN Timing
*( “
Address Reg Points to Pixel Mask Register
Sets the Pixel Mask to All “1s”
Address Reg Points to Command Register 1 (CR1)
Address Reg Points to Command Register 2 (CR2)
Sets 24-Bit Color, 7.5 IRE, SYNC on Green (IOG)
Address Reg Points to Command Register 3 (CR3)
Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/4
Comment
Points to Color Palette RAM
(Initializes Palette RAM
(
(
(
(
(
(
(
(
(
(RAM Initialization Complete
to a Linear Ramp**
REV. B