adv7194 Analog Devices, Inc., adv7194 Datasheet - Page 37

• Manufacturer Part Number: adv7194
• Description: Professional Extended-10? Video Encoder With 54 Mhz Oversampling
• Manufacturer: Analog Devices, Inc.

SUBCARRIER FREQUENCY REGISTERS 3–0
(FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH)
These 8-bit-wide registers are used to set up the Subcarrier Fre-
quency. The value of these registers are calculated by using the
following equation:
Figure 68 shows how the frequency is set up by the four registers.
SUBCARRIER PHASE REGISTER (FPH7–FPH0)
(Address (SR4–SR0) = 10H)
This 8-bit-wide register is used to set up the Subcarrier Phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
SUBCARRIER
SUBCARRIER
SUBCARRIER
SUBCARRIER
SUBCARRIER
Example: NTSC Mode, f
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
REGISTER
Subcarrier Frequency alue
PHASE
REG 0
REG 3
REG 2
REG 1
Subcarrier Frequency
Subcarrier Register Value = 21F07C16 Hex
FSC15
FSC31
FSC23
FSC7
FPH7
FSC14
FSC30
FSC22
FSC6
FPH6
V
CLK
FSC21
FSC13
FSC29
FSC5
FPH5
TIMING MODE 1 (MASTER/PAL)
TR17 TR16
= 27 MHz, f
0
0
1
1
Register =
TR17
HSYNC TO PIXEL
=
DATA ADJUST
VSYNC
HSYNC
FSC12
FSC28
FSC20
FSC4
FPH4
(
1
0
1
0
2
32
0
1
2
3
–
FSC11
FSC27
FSC19
FSC3
FPH3
TR16
1
T
T
T
T
(
)
PCLK
PCLK
PCLK
PCLK
2
SCF
×
32
27
3 5795454
T
= 3.5795454 MHz
LINE 1
–
.
FSC18
FSC10
FSC26
B
FSC2
FPH2
×
f
T
CLK
1
TR15 TR14
A
TR15 TR14
10
)
RISING EDGE DELAY
0
0
1
1
TR15
×
HSYNC TO VSYNC
6
(MODE 2 ONLY)
(MODE 1 ONLY)
VSYNC WIDTH
f
FSC25
FSC17
FSC9
FSC1
FPH1
0
SCF
1
0
1
0
1
×
1
4
16
128
T
T
10
B
B
FSC16
FSC24
FSC0
FSC8
FPH0
T
T
+ 32 s
TR14
T
T
6
PCLK
PCLK
C
PCLK
T
PCLK
TR13 TR12
TR13
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Address (SR4–SR0) = 11–12H)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on Even Fields. Figure 70 shows how the
high and low bytes are set up in the registers.
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
(Subaddress (SR4–SR0) = 13–14H)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on Odd Fields. Figure 71 shows how the high and low
bytes are set up in the registers.
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0
(PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)
(Subaddress (SR4–SR0) = 15–18H)
These 8-bit-wide registers are used to enable the NTSC pedes-
tal/PAL Teletext on a line by line basis in the vertical blanking
interval for both odd and even fields. Figures 68 and 69 show
the four control registers. A Logic 1 in any of the bits of these
registers has the effect of turning the Pedestal OFF on the
equivalent line when used in NTSC. A Logic 1 in any of the
bits of these registers has the effect of turning Teletext ON on
the equivalent line when used in PAL.
0
0
1
1
BYTE 0
BYTE 0
VSYNC DELAY
BYTE 1
HSYNC TO
0
1
0
1
BYTE 1
0
4
8
18
CCD7
CCD7
TR12
CCD15
T
T
T
T
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10
PCLK
PCLK
T
PCLK
B
PCLK
T
CCD6
CCD6
C
LINE 313
CCD14
TR11 TR10
TR11
0
0
1
1
CCD5
CCD5
HSYNC WIDTH
CCD13
1
0
1
0
CCD4
1
4
16
128
CCD4
TR10
LINE 314
CCD12
T
T
T
PCLK
T
PCLK
A
PCLK
T
PCLK
CCD3
CCD3
CCD11
CCD2
CCD2
CCD10
ADV7194
CCD1
CCD1
CCD9
CCD9
CCD0
CCD0
CCD8
CCD8