adv7194 Analog Devices, Inc., adv7194 Datasheet
adv7194
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adv7194 Summary of contents
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... registered trademark of Philips Corporation. Video Encoder with 54 MHz Oversampling GENERAL DESCRIPTION The ADV7194 is part of the new generation of video encoders from Analog Devices. The device builds on the performance of previous video encoders and provides new features like inter- facing progressive scan devices, digital noise reduction, gamma correction, 4× ...
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... ADV7194 CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS 5 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.3 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 V Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 V Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10 DETAILED DESCRIPTION OF FEATURES ...
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... REF . PLL ADV7194 unless MIN MAX Unit Test Conditions Bits LSB LSB Guaranteed Monotonic V V µ 0 2 µA µA = 400 µ SOURCE 3.2 mA SINK µA µ ...
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... DAC I CCT NOTES All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. For 2 × Oversampling Mode, the power 1 requirements for the ADV7194 are typically 3 Temperature range 0°C to 70°C. MIN MAX 3 For all inputs but PAL_NTSC and ALSB ...
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... unless otherwise noted.) MIN MAX Min Typ Max 0.5 0.8 0 0.7 0.5 0.1 0.2 (0.5) 0.5 (0.2) 78.5 (78) 78 (78) 62.3 (62) 61 (62.5) ADV7194 = 1200 unless otherwise noted. All SET1,2 Unit Test Conditions Degrees % ± % Referenced to 40 IRE ± Degrees ± % ± ± Degrees dB rms RMS dB p-p Peak Periodic dB rms ...
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... ADV7194 5 V TIMING CHARACTERISTICS Parameter 2 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time SDATA, SCLOCK Fall Time Setup Time (Stop Condition), t ...
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... MHz 2 Clock Cycles MHz ADV7194 = 1200 unless otherwise noted. All SET1,2 2 Test Conditions After This Period the First Clock Is Generated Relevant for Repeated Start Condition ...
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... ADV7194 SDA SCL CLOCK HSYNC, CONTROL VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, VSYNC, CONTROL BLANK, O/PS CSO_HSO, VSO, CLAMP TTXREQ t 16 CLOCK TTX 4 CLOCK CYCLES CLOCK Y0 – Y9 INCLUDING SYNC INFORMATION Cb0 – Cb9 PROGRESSIVE SCAN INPUT Cr0 – Cr9 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7194 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Video Signals from the DAC Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL. The input resets the on-chip timing generator and sets the ADV7194 into default mode See Appendix 8 for Default Register settings. Dual function CSO or HSO output Sync Signal at TTL level. ...
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... P15 PLL CLKIN CLKOUT There are six DACs available on the ADV7194, each of which is capable of providing 4. current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video, and YUV Video. All YUV formats (SMPTE/EBU N10, MII, or Betacam) are supported. ...
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... Y typically has a range 235, Cr and Cb typically have a range of 128+/–112; however possible to input data from 1 to 254 on both Y, Cb, and Cr. The ADV7194 sup- ports PAL ( and NTSC M, N (with and without Pedestal) and PAL60 standards. ...
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... When used to interface progressive scan systems, the ADV7194 allows input to YCrCb signals in Progressive Scan format (3 × 10 bit) before these signals are routed to the interpolation filters and the DACs. INTERNAL FILTER RESPONSE The Y Filter supports several different frequency responses including two low-pass responses, two notch responses, an Extended (SSAF) response with or without gain boost/attenuation, a CIF response and a QCIF response ...
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... ADV7194 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 – ...
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... ADV7194 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz ...
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... ADV7194 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 – ...
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... CVBS hence the hue is shifted. The ADV7194 provides a range of OUTPUT PIN ± 22° in increments of 0.17578125°. (Hue Adjust Register.) CHROMINANCE CONTROL ...
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... See Appendix 8 for the regis- ter settings after RESET is applied. PROGRESSIVE SCAN INPUT It is possible to input data to the ADV7194 in progressive scan format. For this purpose the input pins Y0/P10–Y9/P19, Cr0–Cr9, Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data and 10-bit Cr data. The data is clocked into the part at 27 MHz. The data is then fi ...
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... The SUBCARRIER PHASE will reset to that of Field 0 at the start of the following field when a low to high transition occurs on this input pin. (c) In RTC MODE, the ADV7194 can be used to lock to an external video source. The real-time control mode allows the ADV7194 to auto- matically alter the subcarrier frequency to compensate for line length variations ...
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... It is possible to operate all six DACs at 27 MHz (2× Oversam- pling MHz (4× Oversampling). The ADV7194 is supplied with a 27 MHz clock synced with the incoming data. Two options are available: to run the device throughout at 27 MHz or to enable the PLL. In the latter case, even if the incoming data runs at 27 MHz, 4× ...
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... TIME SLOT: 01 NOT USED IN ADV7194 NOTES PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7194 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 SC PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7194. 2 SEQUENCE BIT PAL LINE NORMAL LINE INVERTED ...
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... Register 0 TR0 = The ADV7194 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin ...
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... EVEN FIELD ODD FIELD DISPLAY 309 310 311 312 313 314 H V ODD FIELD F EVEN FIELD ANALOG VIDEO VERTICAL BLANK VERTICAL BLANK 318 315 316 317 319 ADV7194 DISPLAY DISPLAY 335 336 320 334 ...
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... In this mode the ADV7194 accepts Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 42 (NTSC) and Figure 43 (PAL). ...
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... Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 45 (NTSC) and Figure 46 (PAL). ...
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... VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 45 (NTSC) and Figure 46 (PAL). Figure 47 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd fi ...
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... In this mode the ADV7194 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is dis- abled the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 49 (NTSC) and Figure 50 (PAL). ...
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... S SLAVE ADDR A(S) SEQUENCE S = START BIT P = STOP BIT The ADV7194 acts as a standard slave device on the bus. The data 2 C-compatible) micro- on the SDA pin is 8 bits long supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress ...
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... REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7194 except the Subaddress Registers which are write only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register ...
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... MR1 BIT DESCRIPTION DAC Control (MR10–MR15) Bits MR15–MR10 can be used to power down the DACs. This are used to reduce the power consumption of the ADV7194 or if any of the DACs are not required in the application. 4 Oversampling Control (MR16) To enable 4× Oversampling this bit has to be set to 1. When enabled, the data is output at a frequency of 54 MHz ...
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... When this bit is set to 1 the video standard is as programmed in Mode Register 0 (Output Video Standard Selection). When it is set to 0, the ADV7194 is forced into the standard selected by the NTSC_PAL pin. When NTSC_PAL is low the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL. ...
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... If MR41 is set to one and MR42 is set to one, the SCRESET/ RTC/TR pin is configured as a real time control input and the ADV7194 can be used to lock to an external video source working in RTC mode. See Figure 37. Active Video Line Duration Control (MR43) This bit switches between two active video line durations ...
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... RGB outputs. Clamp Delay (MR54–MR55) These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7194 possible to delay or advance the pulse by zero, one, two, or three clock cycles. Note: TTX functionality is shared with VSO and CLAMP on Pin 62 ...
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... When this bit is set (0), brightness control is disabled. Sharpness Filter Enable (MR74) This bit is used to enable the sharpness control of the luminance signal on the ADV7194 (Luma Filter Select has to be set to Extended, MR04–MR02 = 100). The various responses of the filter are determined by the Sharpness Control Register. When this bit is set 1, the luma response is altered by the amount described in the Sharpness Control Register ...
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... Gamma Curve Select Bit. Double Buffering is not available in Mastering Timing mode. 20-, 16-Bit Pixel Port (MR83) This bit controls whether the ADV7194 is operated in 16-bit mode (10-Bit Pixel Port disabled, MR84 = 0, MR83 = 1) or 20-bit mode (10-Bit Pixel Port enabled, MR84 =1, MR83 = 1). ...
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... Min Luminance Value (TR06) This bit is used to control the minimum luma output value by the ADV7194. When this bit is set to a Logic 1, the luma is limited to 7IRE below the blank level. When this bit is set to (0), the luma value can be as low as the sync bottom level. ...
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... FPH0 registers has the effect of turning the Pedestal OFF on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of turning Teletext ON on the equivalent line when used in PAL. ADV7194 TR11 TR10 HSYNC WIDTH T TR11 TR10 ...
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... CGMS CRC Check Control (C/W04) When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check sequence, is internally calculated by the ADV7194. If this bit is disabled (0), the CRC values in the reg- ister are output to the CGMS data stream. CGMS Odd Field Control (C/W05) When this bit is set (1), CGMS is enabled for odd fi ...
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... Example: Scale Factor = 1.18 V Scale Value = 1.18 × 128 = 151.04 V Scale Value = 151 (rounded to the nearest integer) V Scale Value = 10010111 V Scale Value = 97 CC17 CC16 CC27 CC26 ADV7194 CC05 CC04 CC03 CC02 CC01 CC07 – CC00 Y SCALE VALUE U Scale Value = Scale Factor × 128 Scale Value = Scale Factor × ...
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... The ADV7194 provides a range of ±22.5° incre- ments of 0.17578125°. For normal operation (zero adjustment) this register is set to 80Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable. Hue Adjust [° ...
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... This bit is used to select the size of the data blocks to be pro- cessed (see Figure 85). Setting the block size control function to a Logic 1 defines a 16 × 16 pixel data block, a Logic 0 defines an 8 × 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz. ADV7194 DNR06 DNR05 DNR04 DNR03 ...
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... ADV7194 DNR17 BLOCK SIZE CONTROL DNR17 0 8 PIXELS 1 16 PIXELS DNR2 BIT DESCRIPTION DNR Input Select (DNR20–DNR22) Three bits are assigned to select the filter which is applied to the incoming Y data. The signal which lies in the passband of the selected filter is the signal which will be DNR processed. Figure 87 shows the fi ...
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... The gamma curves shown above are examples only, any user defined curve is acceptable in the range of 16–240. ADV7194 DNR21 DNR20 DNR INPUT SELECT CONTROL DNR DNR DNR FILTER ...
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... ADV7194 BRIGHTNESS DETECT REGISTER (Address (SR5–SR0) = 34H) The Brightness Detect Register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of the incoming video data on a field-by-field basis. The brightness 2 information is read from the I C and based on this information, the color controls or the gamma correction controls may be adjusted ...
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... AA connected to the regular PCB power plane (V analog power plane. Analog Signal Interconnect The ADV7194 should be located as close as possible to the out- put connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection ...
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... F 0.1 F 48 COMP2 COMP1 REF DAC A 300 Cb0 – Cb9 DAC B Cr0 – Cr9 300 ADV7194 Y0/P10 – Y9/P19 DAC C 300 P9 – P0 DAC D 300 CSO_HSO VSO/TTX/CLAMP DAC E PAL_NTSC 300 SCRESET/RTC/TR DAC F HSYNC 300 VSYNC BLANK SCL RESET ...
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... Scan Line 284. The data for this operation is stored in Closed Captioning Extended Data Registers 0 and 1. All clock run-in signals and timing to support Closed Captioning on Lines 21 and 284 are generated automatically by the ADV7194 All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled. ...
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... C7. If the bit C/W04 is set to a Logic 1, the last six bits C19–C14 which comprise the 6-bit CRC check sequence are calculated auto- matically on the ADV7194 based on the lower 14 bits (C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data ...
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... The ADV7194 supports Wide Screen Signalling (WSS) conform- ing to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7194 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code, see Figure 97. The bits are output from the confi ...
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... APPENDIX 5 TELETEXT INSERTION Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit has a width of almost four clock cycles. The ADV7194 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal which can be output on the CVBS and Y outputs. ...
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... APPENDIX 6 OPTIONAL OUTPUT FILTER filter is not required if the outputs of the ADV7194 are con- nected to most analog monitors or TVs, however, if the output signals are applied to a system where sampling is used (e.g., Digital TVs) then a filter is required to prevent aliasing. FILTER O/P FILTER I/P 600R 0 – ...
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... ADV7194 External buffering is needed on the ADV7194 DAC outputs. The configuration in Figure 105 is recommended. When calculating absolute output full-scale current and voltage use the following equations: × OUT OUT LOAD × K)/ OUT REF K = 4.2146 constant, V REF V AA ADV7194 V REF ...
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... The ADV7194 registers can be set depending on the user standard required. The following examples give the various register for- mats for several video standards. NTSC (F = 3.5795454 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 ...
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... ADV7194 PAL 4.43361875 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register 7 08Hex Mode Register 8 09Hex Mode Register 9 0AHex Timing Register 0 0BHex Timing Register 1 ...
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... Gamma 10 xxHex 31Hex Gamma 11 xxHex 32Hex Gamma 12 xxHex 33Hex Gamma 13 xxHex 34Hex Brightness Detect Register 72Hex 35Hex Output Clock Register ADV7194 (PAL_NTSC = 1, PAL Selected) Data 00Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex ...
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... ADV7194 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 963.8mV 286mV (pk-pk) 650mV 335.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) 629.7mV (pk-pk) 1268.1mV PEAK COMPOSITE 1048.4mV REF WHITE 714.2mV 387.6mV BLACK LEVEL BLANK LEVEL 334 ...
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... IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 286mV (pk-pk) 650mV 283mV 0mV 100 IRE 0 IRE –40 IRE ADV7194 1289.8mV PEAK COMPOSITE REF WHITE 1052.2mV 714.2mV BLANK/BLACK LEVEL 338mV SYNC LEVEL 52.1mV REF WHITE 1052.2mV 714.2mV 338mV BLANK/BLACK LEVEL SYNC LEVEL 52 ...
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... ADV7194 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 990mV 300mV (pk-pk) 650mV 318mV 0mV 1050.2mV 351.8mV 51mV PAL WAVEFORMS PEAK COMPOSITE 696.4mV BLANK/BLACK LEVEL 696.4mV BLANK/BLACK LEVEL 672mV (pk-pk) 698.4mV BLANK/BLACK LEVEL REF WHITE SYNC LEVEL REF WHITE SYNC LEVEL PEAK CHROMA BLANK/BLACK LEVEL ...
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... BLUE (B) 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 0 100 100 200 200 300 300 ADV7194 Pr(C) mV 250 200 150 100 50 0 –50 –100 –150 –200 –250 mV RED (C) 700 600 500 400 300 200 100 ...
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... ADV7194 334mV 171mV BETACAM LEVEL 0mV 171mV 334mV 505mV 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV 232mV SMPTE LEVEL 118mV 0mV –118mV –232mV –350mV UV WAVEFORMS 505mV BETACAM LEVEL 0mV 0mV 467mV BETACAM LEVEL 0mV 0mV 350mV SMPTE LEVEL 0mV 0mV ...
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... SLOW CLAMP TO 0. 6.72 s 0.5 0.0 L575 0.0 10.0 20.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SOUND-IN-SYNC OFF SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED 30.0 40.0 50.0 60.0 MICROSECONDS PRECISION MODE OFF SOUND-IN-SYNC OFF SYNCHRONOUS SYNC = A FRAMES SELECTED: 1 ADV7194 60.0 70.0 ...
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... ADV7194 0.5 0.0 –0.5 L575 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s 100.0 0.5 50.0 0.0 0.0 –50.0 0.0 APL = 44.6% 525 LINE NTSC SLOW CLAMP TO 0. 6.72 s 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING SYNCHRONOUS F1 L76 10.0 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING 50.0 60.0 NO BRUCH SIGNAL SOUND-IN-SYNC OFF ...
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... SLOW CLAMP TO 0. 6.72 s 0.4 50.0 0.2 0.0 –0.2 –50.0 –0.4 F1 L76 0.0 10.0 20.0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0. 6.72 s 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED 30.0 40.0 50.0 60.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED ADV7194 60.0 ...
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... ADV7194 COLOR BAR (NTSC) FIELD = 1 LINE = 21 LUMINANCE LEVEL (IRE) 99.6 69.0 100 50 0 GRAY YELLOW CHROMINANCE LEVEL (IRE) 0.0 62.1 100 50 0 GRAY YELLOW CHROMINANCE PHASE (DEGREE) 167.3 400 200 0 GRAY YELLOW AVERAGE 32 32 COLOR BAR (PAL) LINE = 570 LUMINANCE LEVEL (mV) 695.7 464.8 1000 500 ...
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... AVERAGE 32 LUMINANCE NONLINEARITY (PAL) MOD 5 STEP LINE = 570 LUMINANCE NONLINEARITY (PERCENT) p-p = 0.4 99.6 113 100.0 99.9 111 109 107 105 103 101 AVERAGE 32 ADV7194 WFM MOD 5 STEP MIN = 0.00, MAX = 0.32, p-p = 0.32 0.30 0.15 0.24 0.32 0. MIN = 0.00, MAX = 0.16, p-p = 0.16 0.09 0.13 0.16 0.12 0. ...
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... ADV7194 CHROMINANCE NONLINEARITY(NTSC) WFM FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.5 0 –10 20IRE 40IRE CHROMINANCE PHASE ERROR (DEGREE) –0.0 0 –5 20IRE 40IRE CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714mV) 0.0 0.1 0.2 0.1 0.0 –0.1 –0.2 20IRE 40IRE AVERAGE 32 32 CHROMINANCE AM/PM (NTSC) WFM FIELD = 2, LINE = 217 ...
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... NOISE LEVEL = –63.1dB RMS AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 100kHz TO FULL (TILT NULL) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 ADV7194 WFM NOISE LEVEL = –79.1dB RMS MHz WFM NOISE LEVEL = –62.3dB RMS MHz ...
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... ADV7194 APL = 39. SOUND IN SYNC OFF APL = 45.1% YI –Q SETUP 7.5% APPENDIX 10 VECTOR PLOTS 75% 100 R 100% 75 SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND – SYSTEM LINE L76F1 ANGLE (DEG) 0 ...
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... OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead LQFP (ST-80) 0.640 (16.25) SQ 0.620 (15.75) 0.063 (1.60) 0.553 (14.05) MAX SQ 0.549 (13.95) 0.030 (0.75) 80 0.020 (0.50) 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.004 (0.10) 20 MAX 21 0.006 (0.15) 0.002 (0.05) 0.029 (0.73) 0.014 (0.35) 0.057 (1.45) 0.022 (0.57) 0.010 (0.25) 0.053 (1.35) ADV7194 61 60 0.486 (12.35) TYP ...