adv7194 Analog Devices, Inc., adv7194 Datasheet - Page 34

• Manufacturer Part Number: adv7194
• Description: Professional Extended-10? Video Encoder With 54 Mhz Oversampling
• Manufacturer: Analog Devices, Inc.

ADV7194
MODE REGISTER 6
MR6 (MR67–MR60)
(ADDRESS (SR4–SR0) = 06H)
Mode Register 6 is an 8-bit-wide register. Figure 61 shows the
various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION
Power-Up Sleep Mode Control (MR60)
After RESET is applied this control is enabled (MR60 = 0) if
both SCRESET/RTC/TR and NTSC_PAL pins are tied high.
The ADV7194 will then power up in Sleep Mode to facilitate
low power consumption before the I
this control is disabled (MR60 = 1, via the I
trol passes to Sleep Mode Control, MR27.
PPL Enable Control (MR61)
The PLL control should be enabled (MR61 = 0) when 4×
Oversampling is enabled (MR16 = 1). It is also used to reset the
PLL when this bit is toggled.
Reserved (MR62, MR63, MR64)
A Logic 0 must be written to these bits.
Field Counter (MR65, MR66, MR67)
These three bits are read-only bits. The field count can be read
back over the I
from 0–3, in PAL Mode from 0–7.
MODE REGISTER 7
MR7 (MR77–MR70)
(Address (SR4–SR0) = 07H)
Mode Register 7 is an 8-bit-wide register. Figure 62 shows the
various operations under the control of Mode Register 7.
MR7 BIT DESCRIPTION
Color Control Enable (MR70)
This bit is used to enable control of contrast and saturation of
color. If this bit is set (1) color controls are enabled (Contrast
Control, U-Scale, V-Scale Registers). If this bit is set (0), the color
control features are disabled.
Luma Saturation Control (MR71)
When this bit is set (1), the luma signal will be clipped if it reaches
a limit that corresponds to an input luma value of 255 (after
scaling by the Contrast Control Register). This prevents the
2
C interface. In NTSC mode the field count goes
MR77
MR67 MR66 MR65
OUTPUT CONTROL
MR67
0
1
FIELD COUNTER
CLAMP/ VSO
VSO OUTPUT
CLAMP OUTPUT
MR77
TTX INPUT/CLAMP/VSO
MR76
OUTPUT CONTROL
0
1
MR66
2
OUTPUT
C is initialized. When
TXX INPUT
CLAMP/VSO
MR76
2
C) Sleep Mode con-
MR75
MR65
OUTPUT CONTROL
0
1
CSO_HSO
HSO OUT
CSO OUT
MR75
MR64 MR63 MR62
SHARPNESS FILTER
MR74
MR64
ZERO MUST
BE WRITTEN
TO THESE BITS
0
1
ENABLE
MR74
DISABLE
ENABLE
MR73
MR63
ENABLE CONTROL
0
1
BRIGHTNESS
chrominance component of the composite video signal being
clipped if the amplitude of the luma is too high. When this bit is
set (0), this control is disabled.
Hue Adjust Control (MR72)
This bit is used to enable hue adjustment on the composite and
chroma output signals of the ADV7194. When this bit is set (1),
the hue of the color is adjusted by the phase offset described in
the Hue Adjust Control Register. When this bit is set (0), hue
adjustment is disabled.
Brightness Enable Control (MR73)
This bit is used to enable brightness control on the ADV7194.
The actual brightness level is programmed in the Brightness
Control Register. This value or set-up level is added to the scaled
Y data. When this bit is set (1), brightness control is enabled.
When this bit is set (0), brightness control is disabled.
Sharpness Filter Enable (MR74)
This bit is used to enable the sharpness control of the luminance
signal on the ADV7194 (Luma Filter Select has to be set to
Extended, MR04–MR02 = 100). The various responses of the
filter are determined by the Sharpness Control Register. When
this bit is set 1, the luma response is altered by the amount
described in the Sharpness Control Register. When this bit is
set 0, the sharpness control is disabled. See Internal Filter
Response section.
CSO_HSO Output Control (MR75)
This bit is used to determine whether HSO or CSO TTL output
signal is output at the CSO_HSO pin. If this bit is set 1, then
the CSO TTL signal is output. If this bit is set 0, the HSO TTL
signal is output.
TTX Input/ CLAMP–VSO Output Control (MR76)
This bit controls whether Pin 62 is configured as an output or as
an input pin. A 1 selects Pin 62 to be an output for CLAMP or
VSO functionality. A 0 selects this pin as a TTX input pin.
CLAMP/VSO Select Control (MR77)
This bit is used to select the functionality of Pin 62. Setting this
bit to 1 selects CLAMP as the output signal. A 0 selects VSO
as the output signal. Since this pin is also shared with the TTX
functionality, TTX Input/ CLAMP–VSO Output has to be set
accordingly (MR76).
MR73
DISABLE
ENABLE
MR62
MR72
MR61
0
1
HUE ADJUST
0
1
PLL ENABLE
CONTROL
CONTROL
MR72
DISABLE
ENABLE
ENABLED
DISABLED
MR71
LUMA SATURATION
MR61
0
1
CONTROL
MR71
DISABLE
ENABLE
MR60
POWER-UP SLEEP
MR70
MR60
MODE CONTROL
COLOR CONTROL
0
1
0
1
ENABLE
ENABLED
DISABLED
MR70
DISABLE
ENABLE