tda8026 NXP Semiconductors, tda8026 Datasheet - Page 47

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 47.
V
T
[1]
[2]
TDA8026_1
Product data sheet
Symbol Parameter
Serial data input/output pin: SDA; open-drain
V
V
V
I
I
Serial clock input pin: SCL
V
V
I
I
I
f
t
t
t
t
t
t
t
t
t
t
LH
LL
LIH
IL
2
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
f
SU;STO
amb
DD
IL
IH
OL
IL
IH
C-bus timing; see
= V
I/OUCn pin has an internal 11 k pull-up resistor to V
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
= 25 C unless otherwise specified.
DD(INTF)
LOW-level input
voltage
HIGH-level input
voltage
LOW-level output
voltage
HIGH-level leakage
current
LOW-level leakage
current
LOW-level input
voltage
HIGH-level input
voltage
HIGH-level input
leakage current
LOW-level input
current
SCL clock frequency
bus free time between
a STOP and START
condition
hold time (repeated)
START condition
LOW period of the
SCL clock
HIGH period of the
SCL clock
set-up time for a
repeated START
condition
data hold time
data set-up time
rise time
fall time
set-up time for STOP
condition
Interface signals to microcontroller
= 3.3 V; f
Figure 13
clk(ext)
= 10 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V
Conditions
I
I/O
depending on the pull-up
resistance; input or output
depends on the pull-up
resistance
hold time after which first
clock pulse is generated
both SDA and SCL signals;
10 % to 90 %
both SDA and SCL signals;
90 % to 10 %
OL
= 3 mA
All information provided in this document is subject to legal disclaimers.
…continued
Rev. 1 — 9 March 2010
DD(INTF)
.
[2]
Min
0.7 V
-
-
-
0.7 V
-
-
0
1.3
0.6
1.3
0.6
0.6
0
100
-
-
0.6
0.3
0.3
DD(INTF)
DD(INTF)
Multiple smart card slot interface IC
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
+0.3 V
V
0.3
1
1
+0.3 V
V
1
1
400
-
-
-
-
-
-
-
300
300
-
DD(INTF)
DD(INTF)
TDA8026
DD
© NXP B.V. 2010. All rights reserved.
and V
DD(INTF)
DD(INTF)
+ 0.3
+ 0.3
UP
= 10 F;
47 of 59
Unit
V
V
V
V
V
kHz
ns
ns
ns
ns
A
A
A
A
s
s
s
s
s
s