tda8026 NXP Semiconductors, tda8026 Datasheet - Page 37

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
8.10 Slew rate control
The sequence described in
answered), the microcontroller can start a warm reset by setting WARM bit to logic 1 (see
the bit descriptions in
counter set pin RST
Remark: It is assumed that two card activations will not take place simultaneously on card
slots 2 to 5 because only one I/O
protection on the second ATR counter against starting an activation while a count is
ongoing. The first ATR counter is dedicated to the slot 1. Consequently, it is mandatory to
enable only one slot I/O
one slot to another one, it is mandatory to first disable the slot I/O
enabling the slot I/O
card slots 2 to 5. This allows the ATR counter to be reset between card slot switching
actions. If both pins I/OUC1 and I/OUC2 are connected at the same time, this mandatory
condition also applies to card slot 1.
Slew rate control is embedded for the clock buffer and the I/O
rising and falling edge of the card clock signal can be configured using 2 bits in Register6
of bank 1. The settings based on a 30 pF load capacitance and a V
in
Table 38.
[1]
[2]
The rise and fall time is calculated from 10 % to 90 % and 90 % to 10 % (respectively) of
the signal amplitude. The default setting for CLK_SR[1]/CLK_SR[3] (high) is LOW and
CLK_SR[0]/CLK_SR[2] (low) is HIGH.
Only the falling edge of the card I/O
programmable bits in Register6 of bank 1. The settings based on a 30 pF load
capacitance and a V
Table 39.
[1]
[2]
CLK_SR
L
L
H
H
IO_SR
L
L
H
H
Table
The high slots are define by [1] (slot 1) and [3] (all other slots).
The low slots are define by [0] (slot 1) and [2] (all other slots).
The high slots are define by [1] (slot 1) and [3] (all other slots).
The low slots are define by [0] (slot 1) and [2] (all other slots).
[1]
38.
[1]
(high)
Clock Slew rate
I/O slew rate
(high)
All information provided in this document is subject to legal disclaimers.
(n)
(n)
CC(n)
Table 11 on page 19
to LOW and performs the same timing checks (see
line required. During this transition, no I/O
(n)
Rev. 1 — 9 March 2010
= 5 V are shown in
line at the same time for card slots 2 to 5. When switching from
Section 8.9
CLK_SR
L
H
L
H
IO_SR
L
H
L
H
(n)
[2]
(n)
line is available for these four slots. There is no
[2]
(low)
signal can be configured with the two
(low)
relates to a cold reset. If the card is mute (has not
and
Table 39 on page
Table 22 on page
Multiple smart card slot interface IC
Rise and fall time (ns)
10
7
6
5
Fall time (ns)
67
54
35
17
(n)
37:
line of each card slot. The
(n)
(n)
24). Then, the ATR
CC(n)
lines are enabled for
line in use before
TDA8026
© NXP B.V. 2010. All rights reserved.
= 5 V are shown
Figure
12).
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