tda8026 NXP Semiconductors, tda8026 Datasheet - Page 24

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
8.5.4.1 Bank 1 CSb[7:0] Register0 (address 40h) card slots 3 to 5 bit allocation
8.5.4.2 Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5
8.5.4 Card slots 3 to 5 register descriptions
Table 21.
[1]
[2]
(address 05h) read mode bit descriptions
Table 22.
When at least one of the SUPL, PROT, MUTE and EARLY bits are set to logic 1, the IRQN
pin is driven LOW until the status byte has been read. After power-on, the SUPL bit is set
to logic 1 until the status byte has been read and the IRQN pin is LOW until the voltage
supervisor is deactivated.
Bit
Card slot 3 (address 03h), Card slot 4 (address 04h) and Card slot 5 (address 05h)
Symbol
Access
Symbol
Access
Bit
7
6
5
4
3
2
1
0
Reserved bit position.
See table
information on write mode bits.
Symbol
ACTIVE
EARLY
MUTE
PROT
SUPL
CLKSW
-
STAP
Bank 1 CSb[7:0] Register0 (address 40h) card slots 3 to 5 bit allocation
Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read mode bit descriptions
Table 22
All information provided in this document is subject to legal disclaimers.
VCC1V8
ACTIVE
W
for more detailed information on read mode bits and
R
7
[2]
[2]
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
-
-
Rev. 1 — 9 March 2010
EARLY
I/OEN
set to logic 1: the card is active
set to logic 0: the card is inactive
set to logic 1: during ATR, when the card answers too early
set to logic 0: after reading the byte
set to logic 1: during ATR, when the card does not answer
according to the ISO 7816 time period
set to logic 0: after reading the byte
set to logic 1: during a card session when an overload or
overheating occurs
set to logic 0: after reading the byte
set to logic 1: the supervisor signaled a fault
set to logic 0: after reading the byte
set to logic 1: when the card slot is in Power-down mode and the
clock has switched to
Remark: (f
set to logic 0: when exiting Power-down mode and when the clock
is switched back to f
reserved
gives the value of the corresponding STAPn pin when read
W
R
6
MUTE
W
R
5
osc(int)
REG[1:0]
is the internal oscillator frequency)
PROT
W
R
clk(ext)
4
f
Multiple smart card slot interface IC
osc int
PDWN
SUPL
W
R
3
2
Table 23
CLKSW
5V/3VN
W
R
2
for more detailed
TDA8026
© NXP B.V. 2010. All rights reserved.
WARM
-
W
R
1
[1]
START
STAP
24 of 59
W
R
0