adc12l066civyx National Semiconductor Corporation, adc12l066civyx Datasheet - Page 24

• Manufacturer Part Number: adc12l066civyx
• Description: 12-bit, 66 Msps, 450 Mhz Bandwidth A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Applications Information
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC12L066 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100
mV
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be espe-
cially careful of this during turn on and turn off of power.
The V
be operated from a supply in the range of 1.8V to V
can simplify interfacing to devices and systems operating
with supplies less than V
with reduced V
voltage higher than V
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12L066
between these areas, is required to achieve specified per-
formance.
P-P
DR
.
pin provides power for the output drivers and may
DR
. DO NOT operate the V
D
D
.
. Note, however, that t
FIGURE 6. Driving the Signal Inputs with a Transformer
(Continued)
DR
OD
increases
pin at a
D
. This
24
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close prox-
imity to any of the ADC12L066’s other ground pins.
Capacitive coupling between the typically noisy digital cir-
cuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have sig-
nificant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients dur-
ing clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 100Ω resis-
tors in series with each data output line. Locate these resis-
tors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
20032815