adc12l066civyx National Semiconductor Corporation, adc12l066civyx Datasheet - Page 10

• Manufacturer Part Number: adc12l066civyx
• Description: 12-bit, 66 Msps, 450 Mhz Bandwidth A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

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Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conver-
sion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time that a repeti-
tive digital waveform is high to the total time of one period.
The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (V
present at both signal inputs to the ADC.
CONVERSION LATENCY is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error can also be separated into Positive Gain Error
and Negative Gain Error, which are
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is V
where “n” is the ADC resolution in bits, which is 12 in the
case of the ADC12DL066.
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
through positive full scale (
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC12L066 is guaranteed
not to have any missing codes.
Positive Gain Error = Positive Full-Scale Error − Offset Er-
Negative Gain Error = Offset Error − Negative Full-Scale
Gain Error = Positive Full-Scale Error − Negative Full-
1
⁄
2
LSB below the first code transition)
Scale Error
Error
ror
1
⁄
2
LSB above the last code
CM
) is the d.c. potential
REF
/2
n
,
10
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between
the input voltage (V
negative full scale to the first code and its ideal value of 0.5
LSB. Negative Full-Scale Error can be calculated as:
OFFSET ERROR is the input voltage that will cause a tran-
sition from a code of 01 1111 1111 to a code of 10 0000 0000.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
PIPELINE DELAY (LATENCY) See Conversion Latency
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC12L066, PSRR1 is the ratio of
the change in Full-Scale Error that results from a change in
the d.c. power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a.c. signal riding upon the power
supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral compo-
nents below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dBc, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where f
frequency and f
harmonic frequencies.
SECOND HARMONIC DISTORTION (2ND HARM) is the
difference expressed in dB, between the RMS power in the
input frequency at the output and the power in its 2nd
harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the dif-
ference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd har-
monic level at the output.
1
is the RMS power of the fundamental (output)
2
through f
IN +
− V
10
IN −
are the RMS power in the first 9
) just causing a transition from
1
⁄
2
LSB